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參數(shù)資料
| 型號： | AM53C94JC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 總線控制器 |
| 英文描述： | High Performance SCSI Controller |
| 中文描述： | SCSI BUS CONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 29/63頁 |
| 文件大小： | 455K |
| 代理商： | AM53C94JC |
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P R E L I M I N A R Y
AMD
29
Am53C94/Am53C96
Clock Factor Register (09H) Write
3
Clock Factor Register
CLKFREG
Address: 09
H
Type: Write
7
6
5
4
2
1
0
RES
RES
RES
RES
RES
CLKF2
CLKF1
CLKF0
x
x
x
x
x
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Clock Factor 2:0
16506C-29
The Clock Factor Register (CLKFREG) must be set to
indicate the input frequency range of the device. This
value is crucial for controlling various timings to meet the
SCSI specification. The selector can be calculated by
rounding off the quotient of (Input Clock Frequency in
MHz)/(5 MHz). The device has a frequency range of 10
to 25 MHz.
CLKFREG – Bits 7:3 – RES – Reserved
CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0
The CLKF 2:0 bits specify the binary coded value of the
clock factor. The CLKF 2:0 bits will default to a value of 2
by a hard or soft reset.
Input Clock
Frequency in MHz
CLKF2
CLKF1
CLKF0
0
1
0
10
0
1
1
10.01 to 15
1
0
0
15.01 to 20
1
0
1
20.01 to 25
Forced Test Mode Register (0AH) Write
3
Forced Test Mode Register
FTMREG
Address: 0A
H
Type: Write
7
6
5
4
2
1
0
RES
RES
RES
RES
RES
FHI
FIM
FTM
x
x
x
x
x
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Forced High Impedance Mode
Forced Initiator Mode
Forced Target Mode
16506C-30
The Forced Test Mode Register (FTMREG) is for test
use only. The STE bit in the CNTLREG1 must be set for
the FTMREG to operate.
FTMREG – Bits 7:3 – RES – Reserved
FTMREG – Bit 2 – FHI – Forced High Impedance
Mode
The FHI bit when set places all the output and bidirec-
tional pins into a high impedance state.
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