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Publication#
30918
Issue Date:
November 5, 2003
Rev:
A
Amendment/
0
Am49LV6408M
Stacked Multi-chip Package (MCP) 64 Mbit (4 M x 16 bit) Flash Memory and 8
Mbit (512K x 16-Bit) pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.3 volt
■
High Performance
— Access time as fast as 100ns initial 5 ns page Flash
55 ns pSRAM
■
Package
— 69-Ball FBGA
— Look ahead pinout for simple migration
— 8 x 10 x 1.2 mm
■
Operating Temperature
— –40
°
C to +85
°
C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 3 V for read, erase, and program operations
■
Manufactured on 0.23 μm MirrorBit process
technology
■
SecSi
(Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
■
Flexible sector architecture
— One hundred twenty seven 32 Kword sectors
— Eight 4 Kword boot sectors
■
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
■
Minimum 100,000 erase cycle guarantee per sector
■
20-year data retention at 125
°
C
PERFORMANCE CHARACTERISTICS
■
High performance
— 100 ns access time
— 35 ns page read times
— 0.5 s typical sector erase time
— 22 μs typical write buffer word programming time:
16-word write buffer reduces overall programming
time for multiple-word updates
— 4-word page read buffer
— 16-word write buffer
■
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical initial Page read current; 10 mA typical
intra-Page read current
— 50 mA typical erase/program current
— 1 μA typical standby mode current
SOFTWARE & HARDWARE FEATURES
■
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
■
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— WP#/ACC input:
Write Protect input (WP#) protects top or bottom two
sectors regardless of sector protection settings
ACC (high voltage) accelerates programming time for
higher throughput during system production
— Hardware reset input (RESET#) resets device
pSRAM Features
■
As fast as 55ns access time
■
Power dissipation
— Operating: 23 mA maximum
— Standby: 60 μA maximum at 3.0 V
■
CE1ps# and CE2ps Chip Select
■
Power down features using CE1ps# and CE2ps
■
Data retention supply voltage: 1.5 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0),
UB#s (DQ15–DQ8)