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參數(shù)資料
| 型號： | AM49BDS640AHE8I |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multichip Package (MCP), Flash Memory and pSRAM CMOS 1.8 Volt-only Simultaneous Read/Write |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA89 |
| 封裝： | 10 X 8 MM, FBGA-89 |
| 文件頁數(shù)： | 66/84頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AM49BDS640AHE8I |
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64
Am49BDS640AH
December 5, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A21–A12 are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK.
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The
Configuration Register must be set to the Synchronous Read Mode.
Figure 34.
Synchronous Program Operation Timings: CLK Latched Addresses
OE#
CE#f
Data
Addresses
AVD#
WE#
CLK
V
CC
f
555h
PD
t
WC
t
WPH
t
WP
PA
t
VCS
t
DH
t
CH
In
Progress
t
WHWH1
VA
Complete
VA
Program Command Sequence (last two cycles)
Read Status Data
t
DS
t
AVDP
A0h
t
AS
t
CAS
t
AH
t
AVCH
t
CSW
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