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information contained herein without notice.
2
GaAs MMIC VSAT Power Amplifier, 2.0 W
5.9 - 6.4 GHz
M/A-COM Products
Rev. V4
AM42-0040
ADVANCED: Data Sheets contain information regarding a product M/A-COM is considering for
development. Performance is based on target specifications, simulated results, and/or prototype
measurements. Commitment to develop is not guaranteed.
PRELIMINARY: Data Sheets contain information regarding a product M/A-COM has under develop-
ment. Performance is based on engineering tests. Specifications are typical. Mechanical outline has
been fixed. Engineering samples and/or test data may be available. Commitment to produce in
volume is not guaranteed.
Typical Bias Configuration
4,5,6,7,8
Absolute Maximum Ratings
1,2,3
Parameter
Absolute Maximum
Input Power
+23 dBm
VDD
+12 Volts
VGG
-3 Volts
VDD - VGG
+12 Volts
IDD
1700 mA
Channel Temperature
-40°C to +85°C
Storage Temperature
-65°C to +150°C
1. Exceeding any one or combination of these limits may cause
permanent damage to this device.
2. M/A-COM does not recommend sustained operation near
these survivability limits.
3. Case Temperature (TC) = +25°C.
Electrical Specifications: TA = 25°C, VDD = +9 V, VGG adjusted for IDD = 1050 mA
Parameter
Test Conditions
Units
Min.
Typ.
Max.
Linear Gain
PIN < -10 dBm
dB
27
30
—
Input VSWR
PIN < -10 dBm
Ratio
—
2.3:1
2.7:1
Output VSWR
PIN < -10 dBm
Ratio
—
3.0:1
—
Output Power
PIN = +10 dBm, IDD = 1050 mA Typ.
dBm
31.7
33.0
34.5
Output Power vs. Frequency
PIN = +10 dBm, IDD = 1050 mA Typ.
dB
—
1.0
1.5
Output Power vs. Temperature
(with respect to TA = 25°C)
PIN = +10 dBm, IDD = 1050 mA Typ.
TA = -40°C to +70°C
dB
—
±0.4
—
Drain Bias Current
PIN = +10 dBm
mA
900
1050
1100
Gate Bias Voltage
PIN = +10 dBm, IDD = 1050 mA Typ.
V
-2.4
-1.2
-0.4
Gate Bias Current
PIN = +10 dBm, IDD = 1050 mA Typ.
mA
—
5
20
Thermal Resistance
25°C Heat Sink
°C/W
—
5.6
—
Second Harmonic
PIN = +10 dBm, IDD = 1050 mA Typ.
dBc
—
-35
—
Third Harmonic
PIN = +10 dBm, IDD = 1050 mA Typ.
dBc
—
-45
—
VDET
V
2
—
4. Nominal bias is obtained by first connecting -2.4 volts to pin 5
(VGG), followed by connection +9 volts to pin 10 (VDD).
Note sequence. Adjust VGG for a drain current of 1050 mA
typical.
5. RF ground and thermal interface is the flange (case bottom).
Adequate heat sinking is required.
6. No DC bias voltage appears at the RF ports.
7. For optimum IP3 performance, the VDD bypass capacitors
should be placed within 0.5 inches of the VDD leads.
8. Resistor and capacitors surrounding the amplifier are
suggestions and not included as part of the AM42-0040.