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information contained herein without notice.
2
GaAs MMIC VSAT Power Amplifier 1.4 W
14.0 - 14.5 GHz
M/A-COM Products
Rev. V5
AM42-0002
ADVANCED: Data Sheets contain information regarding a product M/A-COM is considering for
development. Performance is based on target specifications, simulated results, and/or prototype
measurements. Commitment to develop is not guaranteed.
PRELIMINARY: Data Sheets contain information regarding a product M/A-COM has under develop-
ment. Performance is based on engineering tests. Specifications are typical. Mechanical outline has
been fixed. Engineering samples and/or test data may be available. Commitment to produce in
volume is not guaranteed.
Application Schematic 4,5,8,9
Absolute Maximum Ratings 1,2,3
Parameter
Absolute Maximum
VDD
12 Volts
VGG
-10 Volts
RF Input Power
+23 dBm
Channel Temperature
150°C
Storage Temperature
-65°C to +150°C
1. Exceeding any one or combination of these limits may cause
permanent damage to this device.
2. M/A-COM does not recommend sustained operation near
these survivability limits.
3. Case Temperature (TC) = +25°C.
Electrical Specifications: TA = 25°C, VDD = +9 V, VGG = -5.0 V, Z0 = 50
Parameter
Test Conditions
Units
Min.
Typ.
Max.
Linear Gain
PIN < 0 dBm
dB
19
22
—
Input VSWR
PIN < 0 dBm
Ratio
—
2.5:1
2.7:1
Output VSWR
PIN < 0 dBm
Ratio
—
2.7:1
—
Saturated Output Power
PIN = +14 dBm
dBm
30.5
31.5
—
Output Power at P1dB
—
dBm
—
29.5
—
Output IP3
Two +24 dBm output tones @ 1 MHz spacing
dBm
—
39
—
Power Added Efficiency
PIN = +14 dBm
%
—
22
—
Bias Current
PIN = +14 dBm
mA
—
800
1400
Thermal Resistance
25°C Heat Sink
°C/W
—
10
—
Detector Output Voltage
RL = 10 K , POUT = +31 dBm
V
—
+3.5
—
Handling Procedures
Please observe the following precautions to avoid
damage:
Static Sensitivity
Gallium Arsenide Integrated Circuits are sensitive
to electrostatic discharge (ESD) and can be
damaged by static electricity. Proper ESD control
techniques should be used when handling these
devices.
4. Nominal bias is obtained by first connecting –5 volts to pin 4
(VGG), followed by connection +9 volts to pin 6 (VDD). Note
sequence.
5. RF ground and thermal interface is the flange (case bottom).
Adequate heat sinking is required.
6. No DC bias voltage appears at the RF ports.
7. The DC resistance at the input port is an open circuit and at
the output port is a short circuit.
8. For optimum IP3 performance, the VDD bypass capacitors
should be placed within 0.5 inches of pin 6.
9. Resistor and capacitors surrounding the amplifier are
suggestions and not included as part of the AM42-0002.