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參數(shù)資料
| 型號(hào)： | AM41DL3208GB30IT |
| 廠(chǎng)商： | Spansion Inc. |
| 英文描述： | LJT 79C 79#22D PIN RECP |
| 中文描述： | 堆疊式多芯片封裝（MCP）閃存和SRAM |
| 文件頁(yè)數(shù)： | 35/65頁(yè) |
| 文件大?。?/td> | 1288K |
| 代理商： | AM41DL3208GB30IT |
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34
Am41DL3208G
February 13, 2002
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 17 and the following subsec-
tions describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a pro-
gram or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 μs, then that bank returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a
“
0
”
on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a
“
1
”
on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 μs, then
the bank returns to reading array data. If not all se-
lected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0
–
DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ6
–
DQ0 may be still
invalid. Valid data on DQ7
–
DQ0 will appear on suc-
cessive read cycles.
Table 17 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 22
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 5.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7
–
DQ0
Addr = VA
Read DQ7
–
DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 =
“
1
”
because
DQ7 may change simultaneously with DQ5.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM41DL3208GB35IT | Circular Connector; No. of Contacts:79; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM41DL3208GB40IT | LJT 41C 41#20 PIN RECP |
| AM41DL3208GB45IT | LJT 41C 41#20 PIN WALL RECP |
| AM41DL3208GB70I | Circular Connector; No. of Contacts:41; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
| AM41DL3208GB70IT | Circular Connector; No. of Contacts:41; Series:MS27505; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:21; Circular Contact Gender:Socket; Circular Shell Style:Box Mount Receptacle RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM41DL3208GB35IT | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB40IT | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB45IT | 制造商:SPANSION 制造商全稱(chēng):SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM41DL3208GB55IT | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM |
| AM41DL3208GB70I | 制造商:Spansion 功能描述:COMBO 2MX16/4MX8 FLASH + 512KX16/1MX8 SRAM 3V/3.3V 73FBGA - Trays |
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