參數(shù)資料
型號： AM29PL320DT70
廠商： Spansion Inc.
英文描述： 32 Megabit (2 M x 16-Bit/1 M x 32-Bit) CMOS 3.0 Volt-only High Performance Page Mode Flash Memory
中文描述： 32兆位（2米× 16位/ 1個M × 32位）的CMOS 3.0伏，不僅具備高性能頁面模式閃存
文件頁數(shù)： 13/50頁
文件大?。?/td> 947K
代理商： AM29PL320DT70
October 2, 2003
Am29PL320D
11
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the WORD# input determines
whether the device accepts program data in double
words or words. Refer to “Word/Double Word Configu-
ration” for more information.
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required
to program a word or double word, instead of four. The
“Word/Double Word Program Command Sequence”
section has details on programming data to the device
using both standard and Unlock Bypass command
sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 4 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the system asserts V
HH
(11.5 to 12.5 V) on this in-
put, the device automatically enters the aforemen-
tioned Unlock Bypass mode, temporarily unprotects
any protected sectors, and uses the higher voltage on
the pin to reduce the time required for program opera-
tions. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing V
HH
from the ACC pin returns the
device to normal operation. Note that the ACC pin
must not be at V
HH
for operations other than acceler-
ated programming, or device damage may result. In
addition, the ACC pin must not be left floating or un-
connected; inconsistent behavior of the device may re-
sult.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and
I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# input is both held at V
CC
±
0.3 V. (Note that this is
a more restricted voltage range than V
IH
.) If CE# is
held at V
IH
, but not within V
CC
±
0.3 V, the device will
be in the standby mode, but the standby current will be
greater. The device requires standard access time
(t
CE
) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables this
mode when addresses remain stable for t
ACC
+ 30 ns.
The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed.
While in sleep mode, output data is latched and always
available to the system. Note that during Automatic Sleep
mode, OE# must be at V
IH
before the device reduces cur-
rent to the stated sleep mode specification.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output inputs are placed in the high im-
pedance state.
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