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| 型號(hào)： | AM29PDL640G |
| 廠商： | Spansion Inc. |
| 英文描述： | High Speed CMOS Logic 4-Bit Binary Full Adder with Fast Carry 16-CDIP -55 to 125 |
| 中文描述： | 64兆位（4個(gè)M x 16位），3.0伏的CMOS只，同步讀/寫閃存與增強(qiáng)VersatileIO控制記憶 |
| 文件頁(yè)數(shù)： | 36/61頁(yè) |
| 文件大?。?/td> | 1653K |
| 代理商： | AM29PDL640G |
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February 26, 2003
Am29PDL640G
35
P R E L I M I N A R Y
Legend:
DYB = Dynamic Protection Bit
OW = Address (A6:A0) is (0011010)
PD[3:0] = Password Data (1 of 4 portions)
PPB = Persistent Protection Bit
PWA = Password Address. A1:A0 selects portion of password.
PWD = Password Data being verified.
PL = Password Protection Mode Lock Address (A5:A0) is (001010)
RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock status.
SA = Sector Address where security command applies. Address bits
A21:A12 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)
WP = PPB Address (A6:A0) is (0111010) (Note 16)
EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1.
2.
3.
See
Table 1
for description of bus operations.
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock and command cycles, when lower address bits are
555 or 2AAh as shown in table, address bits higher than A11
(except where BA is required) and data bits higher than DQ7 are
don’t cares.
The reset command returns device to reading array.
Cycle 4 programs the addressed locking bit. Cycles 5 and 6
validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0
in cycle 6, program command must be issued and verified again.
Data is latched on the rising edge of WE#.
Entire command sequence must be entered for each portion of
password.
Command sequence returns FFh if PPMLB is set.
10. The password is written over four consecutive cycles, at
addresses 0-3.
4.
5.
6.
7.
8.
9.
11. A 2 μs timeout is required between any two portions of password.
12. A 100 μs timeout is required between cycles 4 and 5.
13. A 1.2 ms timeout is required between cycles 4 and 5.
14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been
fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command
must be issued and verified again. Before issuing erase
command, all PPBs should be programmed to prevent PPB
overerasure.
15. DQ1 = 1 if PPB locked, 0 if unlocked.
16. For all other parts that use the Persistent Protection Bit (excluding
PDL128G), the WP and EP addresses are 00000010.
17. Immediately following successful unlock, write the SecSi Sector
Exit command before attempting to verify, program, or erase the
PPBs.
18. Immediately following the PPB Lock Status command write the
SecSi Sector Exit command before attempting to verify, program,
or erase the PPBs.
Table 15.
Sector Protection Command Definitions
Command (Notes)
C
1
3
4
6
4
4
4
4
6
6
3
4
4
4
4
6
4
6
4
Bus Cycles (Notes 1-4)
Addr Data Addr Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection Bit Program (5, 6)
SecSi Protection Bit Status
Password Program (5, 7, 8)
Password Verify (8, 9)
Password Unlock (7, 10, 11, 17)
PPB Program (5, 6, 12)
All PPB Erase (5, 13, 14)
PPB Lock Bit Set
PPB Lock Bit Status (15, 18)
DYB Write (7)
DYB Erase (7)
DYB Status
PPMLB Program (5, 6, 12)
PPMLB Status (5)
SPMLB Program (5, 6, 12)
SPMLB Status (5)
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
F0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
88
90
60
60
38
C8
28
60
60
78
58
48
48
58
60
60
60
60
XX
OW
OW
XX[0-3]
PWA[0-3] PWD[0-3]
PWA[0-3] PWD[0-3]
(SA)WP
EP
00
68
OW
48
OW
RD(0)
RD(0)
PD[0-3]
68
60
(SA)WP
(SA)EP
48
40
(SA)WP RD(0)
(SA)WP RD(0)
SA
SA
SA
SA
PL
PL
SL
SL
RD(1)
X1
X0
RD(0)
68
RD(0)
68
RD(0)
PL
48
PL
RD(0)
SL
48
SL
RD(0)
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