參數(shù)資料
型號： AM29PDL310G83WHI
廠商： Spansion Inc.
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
中文描述： 64兆位（4個M x 16位），3.0伏的CMOS只，同步讀/寫閃存與增強VersatileIO控制記憶
文件頁數(shù)： 12/61頁
文件大?。?/td> 1653K
代理商： AM29PDL310G83WHI
February 26, 2003
Am29PDL640G
11
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29PDL640G Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 8.5–9.5
V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
High Voltage
Sector Protection
section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC
Read-Only Operations
table for timing
specifications and to Figure 12 for the timing diagram.
I
CC1
in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Random Read (Non-Page Read)
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable ad-
dresses and stable CE# to valid data at the output in-
puts. The output enable access time is the delay from
the falling edge of the OE# to valid data at the output
inputs (assuming the addresses have been stable for
at least t
ACC
–t
OE
time).
Page Mode Read
The device is capable of fast page mode read and is
compatible with the page mode Mask ROM read oper-
ation. This mode provides faster read access speed
for random locations within a page. The page size of
the device is 8 words, with the appropriate page being
selected by the higher address bits A21–A3 and the
LSB bits A2–A0 determining the specific word within
that page. This is an asynchronous operation with the
microprocessor supplying the specific word location.
The random or initial page access is equal to t
ACC
or
t
CE
and subsequent page read accesses (as long as
the locations specified by the microprocessor falls
within that page) is equivalent to t
PACC
. When CE# is
Operation
CE#
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 1)
DQ15–
DQ0
Read
L
L
H
H
X
A
IN
D
OUT
Write
L
H
L
H
X
A
IN
D
IN
Standby
V
IO
±
0.3 V
X
X
V
IO
±
0.3 V
X
X
High-Z
Output Disable
L
H
H
H
X
X
High-Z
Reset
X
X
X
L
X
X
High-Z
Temporary Sector Unprotect (High
Voltage)
X
X
X
V
ID
X
A
IN
D
IN
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