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參數(shù)資料
| 型號： | Am29LV800T-90R |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 3.0 Volt-only, Sectored Flash Memory |
| 中文描述： | 8兆位（1,048,576 x 8-Bit/524，288 x 16位），3.0伏的CMOS只，扇區(qū)閃存 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 207K |
| 代理商： | AM29LV800T-90R |
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10
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
USER BUS OPERATIONS
Read Mode
The Am29LV800 has three control functions which
must be satisfied in order to obtain data at the outputs:
I
CE is the power control and should be used for
device selection (CE = V
IL
I
OE is the output control and should be used to gate
data to the output pins if the device is selected
(OE = V
IL
)
I
WE remains at V
IH
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from stable addresses
and stable CE to valid data at the output pins. The out-
put enable access time (t
OE
) is the delay from the fall-
ing edge of OE to valid data at the output pins
(assuming the addresses have been stable at least
t
ACC
– t
OE
time).
Standby Mode
The Am29LV800 is designed to accommodate two
modes for low standby power consumption. Both
modes are enabled by applying the voltages specified
below to the CE and RESET pins. These modes are
available for either TTL/NMOS or CMOS logic level de-
signs. The first mode, I
CC3
for TTL/NMOS compatible I/
Os (current consumption <1 mA max.), is enabled by
applying a TTL logic level ‘1’ (V
IH
) to the CE control pin
with RESET = V
IH
. I
CC3
for CMOS compatible I/Os
(current consumption <5
μ
A max.), is enabled when a
CMOS logic level ‘1’ (V
CC
±
0.3 V) is applied to the CE
control pin with RESET = V
CC
±
0.3 V. While in the I
CC3
)
standby mode, the data I/O pins remain in the high im-
pedance state independent of the voltage level applied
to the OE input. See the DC Characteristics section for
more details on Standby Modes.
Deselecting CE (CE = V
IH
or V
CC
±
0.3 V, with RESET
= V
IH
or V
CC
±
0.3 V), will put the device into the I
CC3
standby mode. If the device is deselected during an
Embedded Algorithm
operation, it will continue to
draw active power (I
CC2
), prior to entering the standby
mode, until the operation is complete. Subsequent
reselection of the device for active operations
(CE = V
IL
) will commence pursuant to the AC timing
specifications.
Automatic Sleep Mode
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
consumption. This is extremely important in
battery-powered applications. The Am29LV800 auto-
matically enables the low-power, automatic sleep
mode when addresses remain stable for 200 ns. Auto-
matic sleep mode is independent of the CE, WE, and
OE control signals. Typical sleep mode current draw is
200 nA (for CMOS-compatible operation). Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Output Disable
If the OE input is at a logic high level (V
IH
), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.
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