參數(shù)資料
型號： AM29LV642DU50PAE
廠商： Advanced Micro Devices, Inc.
英文描述： 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control
中文描述： 128兆位（8米× 16位）的CMOS 3.0伏特，只有統(tǒng)一閃存部門與VersatileI /輸出⑩控制
文件頁數(shù)： 29/54頁
文件大?。?/td> 520K
代理商： AM29LV642DU50PAE
May 5, 2006 25022A2
Am29LV642D
27
D A T A S H E E T
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 10 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
The device offers accelerated program operations
through the ACC pin. When the system asserts V
HH
on
the ACC pin, the device automatically enters the Un-
lock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command se-
quence. The device uses the higher voltage on the
ACC pin to accelerate the operation.
Note that the
ACC pin must not be at V
HH
for operations other than
accelerated programming, or device damage may re-
sult.
Figure 3 illustrates the algorithm for the program oper-
ation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 10
shows the address and data requirements for the chip
erase command sequence.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table 10 for program command sequence.
相關(guān)PDF資料
PDF描述
AM29LV642DU50PAI 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control
AM29LV642DU90PAE 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control
AM29LV642DU90PAI 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control
AM29LV642D 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
Am29LV642DU12R 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
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