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參數(shù)資料
| 型號： | AM29LV641ML90EI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) MirrorBita?? 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/Oa?? Control |
| 中文描述： | 4M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
| 封裝： | TSOP-48 |
| 文件頁數(shù)： | 13/60頁 |
| 文件大小： | 640K |
| 代理商： | AM29LV641ML90EI |
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December 21, 2005
Am29LV641MH/L
11
D A T A S H E E T
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
Refer to the
DC Characteristics
table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the
AC Characteristics
tables for RESET# pa-
rameters and to Figure 17 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
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