
42
Am29LV640MU
June 12, 2003
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
3. For 1–16 words programmed.
4. Effective write buffer specification is based upon a 16-word write buffer operation.
5. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
6. AC specifications listed are tested with V
IO
= V
CC
. Contact AMD for information on AC operation with V
IO
≠
V
CC.
Parameter
Speed Options
JEDEC
Std.
Description
90R
101
112
120
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
90
100
110
120
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
ASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
ns
t
WLAX
t
AH
Address Hold Time
Min
45
ns
t
AHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
0
ns
t
DVWH
t
DS
Data Setup Time
Min
45
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OEPH
Output Enable High during toggle bit polling
Min
20
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
ns
t
WHDL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Write Buffer Program Operation (Notes 2, 3)
Typ
352
μs
Effective Write Buffer Program Operation, Per
Word (Notes 2, 4)
Typ
22
μs
Accelerated Effective Write Buffer Program
Operation, Per Word (Notes 2, 4)
Typ
17.6
μs
Single Word Program Operation (Note 2, 5)
Typ
100
μs
Accelerated Single Word Programming
Operation (Note 2, 5)
Typ
90
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.5
sec
t
VHH
V
HH
Rise and Fall Time (Note 1)
Min
250
ns
t
VCS
V
CC
Setup Time (Note 1)
Min
50
μs
t
RB
Write Recovery Time from RY/BY#
Min
0
ns
t
BUSY
WE# High to RY/BY# Low
Min
90
100
110
120
ns