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    參數(shù)資料
    型號(hào): AM29LV640ML101EI
    廠商: ADVANCED MICRO DEVICES INC
    元件分類: PROM
    英文描述: 64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control
    中文描述: 4M X 16 FLASH 3V PROM, 100 ns, PDSO56
    封裝: MO-142B, TSOP-56
    文件頁(yè)數(shù): 13/62頁(yè)
    文件大小: 602K
    代理商: AM29LV640ML101EI
    December 14, 2005
    Am29LV640MH/L
    11
    D A T A S H E E T
    Word/Byte Configuration
    The BYTE# pin controls whether the device data I/O
    pins operate in the byte or word configuration. If the
    BYTE# pin is set at logic ‘1’, the device is in word con-
    figuration, DQ0–DQ15 are active and controlled by
    CE# and OE#.
    If the BYTE# pin is set at logic ‘0’, the device is in byte
    configuration, and only data I/O pins DQ0–DQ7 are
    active and controlled by CE# and OE#. The data I/O
    pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
    used as an input for the LSB (A-1) address function.
    VersatileIO
    (V
    IO
    ) Control
    The
    VersatileIO
    (V
    IO
    ) control allows the host system
    to set the voltage levels that the device generates and
    tolerates on CE# and DQ I/Os to the same voltage
    level that is asserted on V
    IO
    . See
    “Ordering Informa-
    tion” on page 9
    for V
    IO
    options on this device.
    For example, a V
    I/O
    of 1.65–3.6 volts allows for I/O at
    the 1.8 or 3 volt levels, driving and receiving signals to
    and from other 1.8 or 3 V devices on the same data
    bus.
    Requirements for Reading Array Data
    To read array data from the outputs, the system must
    drive the CE# and OE# pins to V
    IL
    . CE# is the power
    control and selects the device. OE# is the output con-
    trol and gates array data to the output pins. WE#
    should remain at V
    IH
    .
    The internal state machine is set for reading array data
    upon device power-up, or after a hardware reset. This
    ensures that no spurious alteration of the memory
    content occurs during the power transition. No com-
    mand is necessary in this mode to obtain array data.
    Standard microprocessor read cycles that assert valid
    addresses on the device address inputs produce valid
    data on the device data outputs. The device remains
    enabled for read access until the command register
    contents are altered.
    See “Reading Array Data” for more information. Refer
    to the AC
    Read-Only Operations
    table for timing speci-
    fications and to Figure 14 for the timing diagram. Refer
    to the DC Characteristics table for the active current
    specification on reading array data.
    Page Mode Read
    The device is capable of fast page mode read and is
    compatible with the page mode Mask ROM read oper-
    ation. This mode provides faster read access speed
    for random locations within a page. The page size of
    the device is 4 words/8 bytes. The appropriate page is
    selected by the higher address bits A(max)–A2. Ad-
    dress bits A1–A0 in word mode (A1–A-1 in byte mode)
    determine the specific word within a page. This is an
    asynchronous operation; the microprocessor supplies
    the specific word location.
    The random or initial page access is equal to t
    ACC
    or
    t
    CE
    and subsequent page read accesses (as long as
    the locations specified by the microprocessor falls
    within that page) is equivalent to t
    PACC
    . When CE# is
    deasserted and reasserted for a subsequent access,
    the access time is t
    ACC
    or t
    CE
    . Fast page mode ac-
    cesses are obtained by keeping the “read-page ad-
    dresses” constant and changing the “intra-read page”
    addresses.
    Writing Commands/Command Sequences
    To write a command or command sequence (which in-
    cludes programming data to the device and erasing
    sectors of memory), the system must drive WE# and
    CE# to V
    IL
    , and OE# to V
    IH
    .
    The device features an
    Unlock Bypass
    mode to facili-
    tate faster programming. Once the device enters the
    Unlock Bypass mode, only two write cycles are re-
    quired to program a word or byte, instead of four. The
    “Word/Byte Program Command Sequence” section
    has details on programming data to the device using
    both standard and Unlock Bypass command se-
    quences.
    An erase operation can erase one sector, multiple sec-
    tors, or the entire device.
    Table 2
    indicates the address
    space that each sector occupies.
    Refer to the DC Characteristics table for the active
    current specification for the write mode. The
    AC Char-
    acteristics
    section contains timing specification tables
    and timing diagrams for write operations.
    Write Buffer
    Write Buffer Programming allows the system to write a
    maximum of 16 words/32 bytes in one programming
    operation. This results in faster effective programming
    time than the standard programming algorithms. See
    “Write Buffer” for more information.
    Accelerated Program Operation
    The device offers accelerated program operations
    through the ACC function. This is one of two functions
    provided by the WP#/ACC pin. This function is prima-
    rily intended to allow faster manufacturing throughput
    at the factory.
    If the system asserts V
    HH
    on this pin, the device auto-
    matically enters the aforementioned Unlock Bypass
    mode, temporarily unprotects any protected sectors,
    and uses the higher voltage on the pin to reduce the
    time required for program operations. The system
    would use a two-cycle program command sequence
    as required by the Unlock Bypass mode. Removing
    V
    HH
    from the WP#/ACC pin returns the device to nor-
    mal operation.
    Note that the WP#/ACC pin must not be
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