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參數(shù)資料
| 型號： | Am29LV160MT90 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit 3.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 16兆位（2米× 8位/ 1個M x 16位），3.0伏的MirrorBit只引導扇區(qū)閃存 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 1849K |
| 代理商： | AM29LV160MT90 |
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26
Am29LV160M
25974B0 August 11, 2003
P r e l i m i n a r y
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does
not
require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Tables
10
–
11
show the address and data
requirements for the chip erase command sequence.
Note that the SecSi Sector,
autoselect, and CFI functions are unavailable when an erase operation is in
progress.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a
hardw are reset
during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See
“Autoselect Command Sequence”
for information on these
status bits. When the Embedded Erase algorithm is complete, the device returns
to reading array data and addresses are no longer latched.
Figure 5
illustrates the algorithm for the erase operation. See the
Erase/Program
Operations
tables in
“AC Characteristics”
for parameters, and to
Figure 18
for tim-
ing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is
initiated by writing two unlock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the address of the sector to be
erased, and the sector erase command. Tables
10
–
11
show the address and data
requirements for the sector erase command sequence.
Note that the SecSi Sec-
tor, autoselect, and CFI functions are unavailable when an erase operation is
in progress.
The device does
not
require the system to preprogram the memory prior to erase.
The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 μs begins.
During the time-out period, additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector to all sectors. The
time between these additional cycles must be less than 50 μs, otherwise the last
address and command might not be accepted, and erasure may begin. It is rec-
ommended that processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands
can be assumed to be less than 50 μs, the system need not monitor DQ3.
Any
command other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data.
The system must rewrite the
command sequence and any additional sector addresses and commands.
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