參數(shù)資料
型號: AM29LV017D
廠商: Advanced Micro Devices, Inc.
英文描述: 16 Megabit (2 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
中文描述: 16兆位(2米× 8位)的CMOS 3.0伏特,只有統(tǒng)一部門閃存
文件頁數(shù): 4/45頁
文件大?。?/td> 955K
代理商: AM29LV017D
Am29LV017D
3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5
Special Handling Instructions for FBGA Packages .................. 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8
Table 1. Am29LV017D Device Bus Operations................................ 8
Requirements for Reading Array Data .....................................8
Writing Commands/Command Sequences ..............................8
Program and Erase Operation Status ......................................9
Standby Mode ..........................................................................9
Automatic Sleep Mode .............................................................9
RESET#: Hardware Reset Pin .................................................9
Output Disable Mode ................................................................9
Table 2. Am29LV017D Sector Address Table................................ 10
Autoselect Mode .....................................................................11
Table 3. Am29LV017D Autoselect Codes (High Voltage Method).. 11
Sector Protection/Unprotection ...............................................11
Temporary Sector Unprotect ..................................................11
Figure 1. In-System Sector Protect/Unprotect Algorithms .............. 12
Figure 2. Temporary Sector Unprotect Operation........................... 13
Hardware Data Protection ......................................................13
Low V
CC
Write Inhibit ..............................................................13
Write Pulse “Glitch” Protection ...............................................13
Logical Inhibit ..........................................................................13
Power-Up Write Inhibit ............................................................13
Common Flash Memory Interface (CFI) . . . . . . .14
Table 4. CFI Query Identification String.......................................... 14
Table 5. System Interface String..................................................... 14
Table 6. Device Geometry Definition .............................................. 15
Table 7. Primary Vendor-Specific Extended Query ........................ 15
Command Definitions . . . . . . . . . . . . . . . . . . . . . .16
Reading Array Data ................................................................16
Reset Command .....................................................................16
Autoselect Command Sequence ............................................16
Byte Program Command Sequence .......................................16
Unlock Bypass Command Sequence .....................................17
Figure 3. Program Operation .......................................................... 17
Chip Erase Command Sequence ...........................................17
Sector Erase Command Sequence ........................................18
Erase Suspend/Erase Resume Commands ...........................18
Figure 4. Erase Operation............................................................... 19
Command Definitions .............................................................20
Table 8. Am29LV017D Command Definitions ............................... 20
Write Operation Status . . . . . . . . . . . . . . . . . . . . .21
DQ7: Data# Polling .................................................................21
Figure 5. Data# Polling Algorithm ................................................... 21
RY/BY#: Ready/Busy# ...........................................................22
DQ6: Toggle Bit I ....................................................................22
DQ2: Toggle Bit II ...................................................................22
Reading Toggle Bits DQ6/DQ2 ...............................................22
Figure 6. Toggle Bit Algorithm........................................................ 23
DQ5: Exceeded Timing Limits ................................................24
DQ3: Sector Erase Timer .......................................................24
Table 9. Write Operation Status..................................................... 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 7. Maximum Negative Overshoot Waveform...................... 25
Figure 8. Maximum Positive Overshoot Waveform........................ 25
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. I
CC1
Current vs. Time (Showing Active
and Automatic Sleep Currents)...................................................... 27
Figure 10. Typical I
CC1
vs. Frequency........................................... 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11. Test Setup..................................................................... 28
Table 10. Test Specifications ......................................................... 28
Figure 12. Input Waveforms and Measurement Levels ................. 28
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Operations ....................................................................29
Figure 13. Read Operations Timings............................................. 29
Hardware Reset (RESET#) ....................................................30
Figure 14. RESET# Timings .......................................................... 30
Erase/Program Operations .....................................................31
Figure 15. Program Operation Timings.......................................... 32
Figure 16. Chip/Sector Erase Operation Timings .......................... 32
Figure 17. Data# Polling Timings (During Embedded Algorithms). 33
Figure 18. Toggle Bit Timings (During Embedded Algorithms)...... 34
Figure 19. DQ2 vs. DQ6................................................................. 34
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 35
Figure 21. Sector Protect/Unprotect Timing Diagram.................... 36
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 39
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 39
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 40
TS 040—40-Pin Standard TSOP ............................................40
TSR040—40-Pin Reverse TSOP ...........................................41
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm package ..................................................................42
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision A (October 1997) .....................................................43
Revision B (October 1997) .....................................................43
Revision C (January 1998) .....................................................43
Revision C+1 (February 1998) ...............................................43
Revision C+2 (March 1998) ....................................................43
Revision C+3 (August 1998) ...................................................43
Revision D (January 1999) .....................................................43
Revision D+1 (April 12, 1999) .................................................43
Revision E (February 2, 2000) ................................................43
Revision E+1 (November 7, 2000) .........................................44
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