• 參數(shù)資料
    型號(hào)： AM29LV017B-90WCE
    廠商： ADVANCED MICRO DEVICES INC
    元件分類： PROM
    英文描述： LM3485/LM3485Q Hysteretic PFET Buck Controller; Package: MINI SOIC; No of Pins: 8; Qty per Container: 1000; Container: Reel
    中文描述： 2M X 8 FLASH 3V PROM, 90 ns, PBGA48
    封裝： 8 X 9 MM, 0.80 MM PITCH, FBGA-48
    文件頁(yè)數(shù)： 7/39頁(yè)
    文件大?。?/td> 510K
    代理商： AM29LV017B-90WCE
    7
    Am29LV017B
    P R E L IM IN A R Y
    DEVICE BUS OPERATIONS
    This section describes the requirements and use of the
    device bus operations, which are initiated through the
    internal command register. The command register itself
    does not occupy any addressable memory location.
    The register is composed of latches that store the com-
    mands, along with the address and data information
    needed to execute the command. The contents of the
    register serve as inputs to the internal state machine.
    The state machine outputs dictate the function of the
    device. Table 1 lists the device bus operations, the in-
    puts and control levels they require, and the resulting
    output. The following subsections describe each of
    these operations in further detail.
    Table 1.
    Am29LV017B Device Bus Operations
    Legend:
    L = Logic Low = V
    IL
    , H = Logic High = V
    IH
    , V
    ID
    = 12.0
    ±
    0.5 V, X = Don’t Care, A
    IN
    = Address In, D
    IN
    = Data In, D
    OUT
    = Data Out
    Note:
    The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
    Protection/Unprotection” section.
    Requirements for Reading Array Data
    To read array data from the outputs, the system must
    drive the CE# and OE# pins to V
    IL
    . CE# is the power
    control and selects the device. OE# is the output con-
    trol and gates array data to the output pins. WE#
    should remain at V
    IH
    .
    The internal state machine is set for reading array data
    upon device power-up, or after a hardware reset. This
    ensures that no spurious alteration of the memory con-
    tent occurs during the power transition. No command is
    necessary in this mode to obtain array data. Standard
    microprocessor read cycles that assert valid addresses
    on the device address inputs produce valid data on the
    device data outputs. The device remains enabled for
    read access until the command register contents are
    altered.
    See “Reading Array Data” for more information. Refer
    to the AC Read Operations table for timing specifica-
    tions and to Figure 13 for the timing diagram. I
    CC1
    in
    the DC Characteristics table represents the active cur-
    rent specification for reading array data.
    Writing Commands/Command Sequences
    To write a command or command sequence (which in-
    cludes programming data to the device and erasing
    sectors of memory), the system must drive WE# and
    CE# to V
    IL
    , and OE# to V
    IH
    .
    The device features an
    Unlock Bypass
    mode to facil-
    itate faster programming. Once the device enters the
    Unlock Bypass mode, only two write cycles are re-
    quired to program a byte, instead of four. The “Byte
    Program Command Sequence” section has details on
    programming data to the device using both standard
    and Unlock Bypass command sequences.
    An erase operation can erase one sector, multiple sec-
    tors, or the entire device. Table 2 indicates the address
    space that each sector occupies. A “sector address”
    consists of the address bits required to uniquely select
    a sector. The “Command Definitions” section has de-
    tails on erasing a sector or the entire chip, or suspend-
    ing/resuming the erase operation.
    After the system writes the autoselect command se-
    quence, the device enters the autoselect mode. The
    system can then read autoselect codes from the inter-
    nal register (which is separate from the memory array)
    on DQ7–DQ0. Standard read cycle timings apply in this
    Operation
    CE#
    L
    L
    V
    CC
    ±
    0.3 V
    L
    X
    OE#
    L
    H
    WE#
    H
    L
    RESET#
    H
    H
    V
    CC
    ±
    0.3 V
    H
    L
    Addresses
    A
    IN
    A
    IN
    DQ0–DQ7
    D
    OUT
    D
    IN
    Read
    Write
    Standby
    X
    X
    X
    High-Z
    Output Disable
    Reset
    H
    X
    H
    X
    X
    X
    High-Z
    High-Z
    Sector Protect (See Note)
    L
    H
    L
    V
    ID
    Sector Addresses,
    A6 = L, A1 = H, A0 = L
    Sector Addresses
    A6 = H, A1 = H, A0 = L
    A
    IN
    D
    IN
    , D
    OUT
    Sector Unprotect (See Note)
    L
    H
    L
    V
    ID
    D
    IN
    , D
    OUT
    Temporary Sector Unprotect
    X
    X
    X
    V
    ID
    D
    IN
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