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| 型號： | AM29LV004BT-120FI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | SWITCH KEYLOCK SP3T 4A 45DEG |
| 中文描述： | 512K X 8 FLASH 3V PROM, 120 ns, PDSO40 |
| 封裝： | REVERSE, MO-142CD, TSOP-40 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 769K |
| 代理商： | AM29LV004BT-120FI |
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14
Am29LV004B
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Tables 2 and 3 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is
not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
Table 5 shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset
immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to the device faster than using the stan-
dard program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. The device
then returns to reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
相關(guān)PDF資料 |
PDF描述 |
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| AM29LV004BB-70EC | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 180pF; Working Voltage (Vdc)[max]: 500V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: X7R; Lead Style: Radial Leaded; Lead Dimensions: 0.100" Lead Spacing; Body Dimensions: 0.150" x 0.210" x 0.130"; Container: Bag; Qty per Container: 500 |
| Am29LV004BT-70EE | Ceramic Conformally Coated / Radial 'Standard & High Voltage Golden Max'; Capacitance [nom]: 200pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic, Conformally Coated; Temperature Coefficient: C0G (NP0); Lead Style: Radial Leaded; Lead Dimensions: 0.100" Lead Spacing; Body Dimensions: 0.150" x 0.210" x 0.130"; Container: Bag; Qty per Container: 500 |
| AM29LV004BB-120EC | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV004BB-120EE | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| AM29LV004BB-120EI | 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM29LV004BT-90EI | 制造商:Advanced Micro Devices 功能描述: |
| AM29LV008BB-120ECT | 制造商:Spansion 功能描述:IC 8MEG X8, 3 V FLASH BOTTOM B |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:IC SM FLASH 3V 8MB |
| AM29LV008BB-120ED | 制造商:Spansion 功能描述:FLASH MEMORY IC |
| AM29LV008BB-80EC | 制造商:Spansion 功能描述:IC 8MEG X8, 3 V FLASH BOTTOM B - Bulk |
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