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參數(shù)資料
| 型號： | AM29LV002BT-90EF |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:2Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 256K X 8 FLASH 3V PROM, 90 ns, PDSO40 |
| 封裝： | LEAD FREE, MO-142BCD, TSOP-40 |
| 文件頁數(shù)： | 7/41頁 |
| 文件大?。?/td> | 687K |
| 代理商： | AM29LV002BT-90EF |
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21520D5 October 11, 2006
Am29LV002B
13
D A TA SH EE T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 defines the valid register command
sequences. Writing incorrect address and data
values or writing them in the improper sequence
resets the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h returns 01h if
that sector is protected, or 00h if it is unprotected. Refer
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles, followed by the
program set-up command. The program address and
data are written next, which in tur n initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell margin.
Table 5 shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
相關PDF資料 |
PDF描述 |
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| AM29LV004BB-120ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV004BB-120EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:120ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV004BB-70ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV004BB-70EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| AM29LV004BB-90ED | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:4Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:3V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM29LV002BT-90EI\\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
| AM29LV002BT-90EI\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
| AM29LV002T-120EC | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 3V/3.3V 2M-Bit 256K x 8 120ns 40-Pin TSOP |
| AM29LV004BB-120EC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 512K x 8, 40 Pin, Plastic, TSSOP |
| AM29LV004BB-120EI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Advanced Micro Devices 功能描述:NOR Flash, 512K x 8, 40 Pin, Plastic, TSSOP |
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