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參數(shù)資料
| 型號： | Am29LV002B-100EIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 2兆位（256畝× 8位），3.0伏的CMOS只，引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 448K |
| 代理商： | AM29LV002B-100EIB |
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Am29LV002
7
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV002 Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 12 for the timing waveforms. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector ad-
dress” consists of the address bits required to uniquely
select a sector. See the “Command Definitions” section
for details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The AC
Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Operation
CE#
L
L
V
CC
±
0.3 V
L
X
X
OE#
L
H
WE#
H
L
RESET#
H
H
V
CC
±
0.3 V
H
L
V
ID
Addresses
A
IN
A
IN
DQ0–DQ7
D
OUT
D
IN
Read
Write
Standby
X
X
X
High-Z
Output Disable
Reset
Temporary Sector Unprotect
H
X
X
H
X
X
X
X
High-Z
High-Z
D
IN
A
IN
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|---|---|
| AM29LV002BB-90EC | 制造商:Advanced Micro Devices 功能描述: |
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| AM29LV002BT-90EI\T | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 2MBIT 256KX8 90NS 40TSOP - Tape and Reel |
| AM29LV002T-120EC | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 3V/3.3V 2M-Bit 256K x 8 120ns 40-Pin TSOP |
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