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參數(shù)資料
| 型號： | AM29F800T-120SI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| 中文描述： | 512K X 16 FLASH 5V PROM, 120 ns, PDSO44 |
| 封裝： | SOP-44 |
| 文件頁數(shù)： | 18/41頁 |
| 文件大?。?/td> | 267K |
| 代理商： | AM29F800T-120SI |
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18
Am29F800T/Am29F800B
8/18/97
P R E L I M I N A R Y
will be automatically reset to read mode and this will
enable the system’s microprocessor to read the
boot-up firmware from the Flash memory.
Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word
(16 bit) mode for the Am29F800 device. When this pin is
driven high, the device operates in the word (16 bit)
mode. The data is read and programmed at DQ0–
DQ15. When this pin is driven low, the device operates
in byte (8 bit) mode. Under this mode, the DQ15/A-1 pin
becomes the lowest address bit and DQ8–DQ14 bits are
tri-stated. However, the command bus cycle is always
an 8-bit operation and hence commands are written at
DQ0–DQ7 and the DQ8–DQ15 bits are ignored. Refer
to Figures 15 and 16 for the timing diagram.
Data Protection
The Am29F800 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power tran-
sitions. During power up the device automatically re-
sets the internal state machine in the Read mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific multi-bus cycle command sequences.
The device also incorporates several features to pre-
vent inadvertent write cycles resulting from V
CC
power-up and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up
and power-down, the Am29F800 locks out write cycles
for V
CC
< V
LKO
(see DC Characteristics section for volt-
ages). When V
CC
< V
LKO
, the command register
is disabled, all internal program/erase circuits are dis-
abled, and the device resets to the read mode. The
Am29F800 ignores all writes until V
CC
> V
LKO
. The
user must ensure that the control pins are in the correct
logic state when V
CC
> V
LKO
to prevent unintentional
writes.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
,
CE = V
IH
, or WE = V
IH
. To initiate a write cycle CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and
OE = V
IH
will not accept commands on the rising edge
of WE. The internal state machine is automatically
reset to the read mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F800T-120SIB | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F800T-150 | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F800T-150EC | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F800T-150ECB | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
| AM29F800T-150EE | 8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
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