- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366426 > AM29F040B-90PD (ADVANCED MICRO DEVICES INC) 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory PDF資料下載
參數(shù)資料
| 型號： | AM29F040B-90PD |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| 中文描述： | 512K X 8 FLASH 5V PROM, 90 ns, PDIP32 |
| 封裝： | LEAD FREE, PLASTIC, MO-015AP, DIP-32 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 534K |
| 代理商： | AM29F040B-90PD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
November 1, 2006 21445E5
Am29F040B
11
D A T A S H E E T
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read shows that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note:
See the appropriate Command Definitions table for
program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See
“Write
Operation Status”
for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched.
Figure
2
illustrates the algorithm for the erase opera-
tion. See the Erase and Program Operations tables in
“AC Characteristics”
for parameters, and to the Chip/
Sector Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 μs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
μs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sec-
tor erase commands can be assumed to be less than
50 μs, the system need not monitor DQ3.
Any com-
mand other than Sector Erase or Erase Suspend
during the time-out period resets the device to
reading array data.
The system must rewrite the com-
mand sequence and any additional sector addresses
and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the
“DQ3: Sector Erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F040B-90PE | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F040B-90PF | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F040B-90PI | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F040B-90PK | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory |
| AM29F040 | 4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only, Sector Erase Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F040B-90PF | 制造商:Spansion 功能描述:IC 5V 4M BIT FLASH SECTOR CS39 |
| AM29F080B-120EC | 制造商:Advanced Micro Devices 功能描述: |
| AM29F080B-120EF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M x 8bit 120ns 40-Pin TSOP |
| AM29F080B-120SC | 制造商:Spansion 功能描述:IC,EEPROM,NOR FLASH,1MX8,CMOS,SOP,44PIN,PLASTIC |
| AM29F080B-120SC/T | 制造商:Spansion 功能描述:FLASH PARALLEL 5V 8MBIT 1MX8 120NS 44SOIC - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。