
22
Am29F040B
P R E L I M I N A R Y
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
t
CH
PA
Note:
PA = program address, PD = program data, D
OUT
is the true data at the program address.
21445B-14
Figure 9.
Program Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
Note:
SA = Sector Address. VA = Valid Address for reading status data.
21445B-15
Figure 10.
Chip/Sector Erase Operation Timings