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參數(shù)資料
| 型號： | Am29F002T-55EIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 2兆位（256畝× 8位）的CMOS 5.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 12/37頁 |
| 文件大小： | 436K |
| 代理商： | AM29F002T-55EIB |
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12
Am29F002/Am29F002N
P R E L IM IN A R Y
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. On the
Am29F002 only, note that a
hardware reset
during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1”.
Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Note:
See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. On the Am29F002
only, note that a
hardware reset
during the sector
erase operation immediately terminates the operation.
The Sector Erase command sequence should be rein-
itiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not
require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50
μ
s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50
μ
s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20818C-5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am29F002NT-55EIB | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F002B-55EIB | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F002T-55JEB | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F002NT-55JEB | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F002B-55JEB | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F002T-55JC | 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:256K X 8 FLASH 5V PROM, 55 ns, PQCC32 |
| AM29F004BB-55JI | 制造商:Advanced Micro Devices 功能描述:Flash Mem Parallel 5V 4M-Bit 512K x 8 55ns 32-Pin PLCC |
| AM29F010 | 制造商:Panasonic Industrial Company 功能描述:IC |
| AM29F010-120DGC1 | 制造商:Spansion 功能描述:1M FLASH KNOWN GOOD DIE (COMMERCIAL TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
| AM29F010-120DGE1 | 制造商:Spansion 功能描述:1M FLASH KNOWN GOOD DIE (EXTEND TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
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