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參數(shù)資料
| 型號： | Am29F002B-120PCB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | High Speed CMOS Logic Non-Inverting Quad 2-Input Multiplexer with 3-State Outputs 16-CDIP -55 to 125 |
| 中文描述： | 2兆位（256畝× 8位）的CMOS 5.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 3/40頁 |
| 文件大小： | 792K |
| 代理商： | AM29F002B-120PCB |
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Am29F002B/Am29F002NB
November 28, 2000
GENERAL DESCRIPTION
The Am29F002B Family consists of 2 Mbit, 5.0
volt-only Flash memory devices organized as 262,144
bytes. The Am29F002B offers the RESET# function,
the Am29F002NB does not. The data appears on
DQ7–DQ0. The device is offered in 32-pin PLCC,
32-pin TSOP, and 32-pin PDIP packages. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt V
CC
supply. No V
PP
is required for
write or erase operations. The device can also be pro-
grammed in standard EPROM programmers.
This device is manufactured using AMD’s 0.32 μm
process technology, and offers all the features and
benefits of the Am29F002, which was manufactured
using 0.5 μm process technology.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard
. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits
. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
(This feature is not available on the Am29F002NB.)
The system can place the device into the
standby mode
.
Power consumption is greatly reduced in this mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F002B-120PE | High Speed CMOS Logic Non-Inverting Quad 2-Input Multiplexer with 3-State Outputs 16-CDIP -55 to 125 |
| Am29F002B-120PEB | High Speed CMOS Logic Inverting Quad 2-Input Multiplexer with 3-State Outputs 16-CDIP -55 to 125 |
| AM29F002B-120PI | High Speed CMOS Logic Inverting Quad 2-Input Multiplexer with 3-State Outputs 16-CDIP -55 to 125 |
| Am29F002B-120PIB | High Speed CMOS Logic 8-Bit Addressable Latch 16-CDIP -55 to 125 |
| Am29F002B-55ECB | High Speed CMOS Logic 8-Bit Addressable Latch 16-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F002B-70JC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 256K x 8, 32 Pin, Plastic, PLCC |
| AM29F002BB-120EC | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, TSOP32, COM - Trays |
| AM29F002BB-120JCT | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, PLCC32, COM, T&R - Tape and Reel |
| AM29F002BB-55EC | 制造商:Spansion 功能描述: |
| AM29F002BB-55JF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K x 8bit 55ns 32-Pin PLCC |
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