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參數(shù)資料
| 型號： | AM29BL802C90RZI |
| 廠商： | Spansion Inc. |
| 英文描述： | 8 Megabit (512 K x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory |
| 中文描述： | 8兆位（512畝× 16位）的CMOS 3.0伏特，只有突發(fā)模式閃存 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大小： | 466K |
| 代理商： | AM29BL802C90RZI |
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November 3, 2006 22371C7
Am29BL802C
15
D A T A S H E E T
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data Array in
Asynchronous (Non-Burst) Mode” in the “Key to Switch-
ing Waveforms” section for more information. The Read
Operations table provides the read parameters, and Fig-
ure 15 shows the timing diagram.
Reading Array Data in Burst Mode
The device powers up in the non-burst mode. To read
array data in burst mode, the system must write the
four-cycle Burst Mode Enable command sequence
(see Table 4). The device then enters burst mode. In
addition to asserting CE#, OE#, and WE# control sig-
nals, burst mode operation requires that the system
provide appropriate LBA#, BAA#, and CLK signals. For
successful burst mode reads, the following events must
occur (refer to Figures 3 and 4 for this discussion):
1. The system asserts LBA# low, indicating to the de-
vice that a valid initial burst address is available on
the address bus. LBA# must be kept low until at
least the next rising edge of the CLK signal, upon
which the device loads the initial burst address.
2. The system returns LBA# to a logic high. The device
requires that the next rising edge of CLK occur with
LBA# high for proper burst mode operation. Typi-
cally, the initial number of CLK cycles depends on
the clock frequency and the rated speed of the de-
vice.
3. After the initial data has been read, the system as-
serts BAA# low to indicate it is ready to read the re-
maining burst read cycles. Each successive rising
edge of the CLK signal then causes the flash device
to increment the burst address and output sequen-
tial burst data.
4. When the device outputs the last word of data in the
32-word burst mode read sequence, the device out-
puts a logic low on the IND# pin. This indicates to
the system that the burst mode read sequence is
complete.
5. To exit the burst mode, the system must write the
four-cycle Burst Mode Disable command sequence.
The device will also exit the burst mode if powered
down or if RESET# is asserted. The device will not
exit the burst mode if the reset command is written.
Figure 3.
Burst Mode Read with 40 MHz CLK, 65 ns t
IACC
, 18 ns t
BACC
Parameters
CLK
LBA#
BAA#
Data
OE#
Step 1
Step 2
Step 3
25 ns
25 ns
25 ns
25 ns
65 ns
25 ns
18 ns
Da
Da +1
Da +2
18 ns
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