參數(shù)資料
型號(hào)： AM29BL162CB70RZI
廠商： Spansion Inc.
英文描述： 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
中文描述： 16兆位（1米× 16位）的CMOS 3.0伏特，只有突發(fā)模式閃存
文件頁(yè)數(shù)： 21/50頁(yè)
文件大?。?/td> 486K
代理商： AM29BL162CB70RZI
July 8, 2005
Am29BL162C
19
D A T A S H E E T
This method is an alternative to that shown in
Table 1
,
which is intended for PROM programmers and requires
V
ID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address 00h retrieves the manufacturer
code. A read cycle at address 01h returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode returns 0001h if that
sector is protected, or 0000h if it is unprotected. Refer
to
Table 2
for valid sector addresses. A read cycle at
address 03h returns 0000h if the device is in asynchro-
nous mode, or 0001h if in synchronous (burst) mode.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is notrequired to provide further
controls or timings. The device automatically gener-
ates the program pulses and verifies the programmed
cell margin.
Table 8
shows the address and data re-
quirements for the program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “
Write Operation Status”
for in-
formation on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset
immediately terminates the program-
ming operation.
Programming is allowed in any sequence and across
sector boundaries.
A bit cannot be programmed
from a “0” back to a “1.”
Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read shows that the
data is still “0.” Only erase operations convert a “0” to a
“1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram words to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time.
Table 8
shows the requirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 5
illustrates the algorithm for the program oper-
ation. See the
Erase/Program Operations
table in “
AC
Characteristics”
for parameters, and to
Figure 18
for
timing diagrams.
相關(guān)PDF資料
PDF描述
AM29BL162CB70RZK 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
AM29BL162CB-90R 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
AM29BL162CB90RZE 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
AM29BL162CB90RZF 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
AM29BL162CB90RZI 16 Megabit (1 M x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
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