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| 型號(hào)： | AM29BDS64HE9VKI |
| 廠商： | Spansion Inc. |
| 英文描述： | 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 128或64兆位（8米或4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存 |
| 文件頁(yè)數(shù)： | 49/89頁(yè) |
| 文件大?。?/td> | 913K |
| 代理商： | AM29BDS64HE9VKI |
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May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
47
D A T A S H E E T
Table 21.
Sector Protection Command Definitions
Legend:
X = Don’t care
PA = Address of the memory location to be programmed. Addresses latch
on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits Amax–A12 uniquely select any sector.
BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for
which command is being written.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
OW = Address (A7–A0) is (00011010).
PD3–PD0 = Password Data. PD3–PD0 present four 16 bit combinations
that represent the 64-bit password.
PWA = Password Address. Address bits A1 and A0 are used to select
each 16-bit portion of the 64-bit entity.
PL = Address (A7–A0) is (00001010)
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 1.
If unprotected, DQ0 = 0.
RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 1.
If unprotected, DQ1 = 0.
SBA = Sector address block to be protected.
SL = Address (A7–A0) is (00010010)
WD= Write Data. See “Configuration Register” definition for specific write
data
WP = Address (A7–A0) is (00000010)
WPE = Address (A7–A0) is (01000010)
Notes:
1.
2.
3.
4.
See Table 1 for description of bus operations.
All values are in hexadecimal.
Shaded cells indicate read cycles. All others are write cycles.
Data bits DQ15–DQ8 are don’t care in command sequences, except
for RD, PD, WD, PWD, and PD3–PD0.
Unless otherwise noted, address bits Amax–A12 are don’t cares.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. The
system must write the reset command to return the device to
reading array data.
No unlock or command cycles required when bank is reading array
data.
Not supported in Synchronous Read Mode, command mode verify
are always asynchronous read operations.
5.
6.
7.
8.
9.
The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
10. The fourth cycle erases all PPBs. The fifth and sixth cycles are used
to validate whether the bits have been fully erased. If DQ0 (in the
sixth cycle) reads 1, the erase command must be issued and verified
again.
11. The entire four bus-cycle sequence must be entered for each portion
of the password.
12. Before issuing the erase command, all PPBs should be programmed
in order to prevent over-erasure of PPBs.
13. In the fourth cycle, 01h indicates PPB set; 00h indicates PPB not
set.
Command Sequence
(Notes)
C
Bus Cycles (Notes 1–6)
First
Second
Third
Fourth
Fifth
Sixth
Seventh
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
S
Entry
3
555
AA
2AA
55
555
88
Exit
4
555
AA
2AA
55
555
90
XX
00
Protection Bit
Program (8, 9)
6
555
AA
2AA
55
555
60
SA+OW
68
SA+OW
48
OW
RD(0)
P
Program (11)
4
555
AA
2AA
55
555
38
XX[0–3]
PD[0–3]
Verify (11)
4
555
AA
2AA
55
555
C8
XX[0–3]
PD[0–3]
Unlock (11)
7
555
AA
2AA
55
555
28
XX0
PD0
XX1
PD1
XX2
PD2
XX3
PD3
P
Program (8, 9)
6
555
AA
2AA
55
555
60
SBA+WP
68
SBA+WP
48
XX
RD(0)
All Erase
(8, 10, 12)
6
555
AA
2AA
55
555
60
WPE
60
SBA+
WPE
40
XX
RD(0)
Status (13)
4
555
AA
2AA
55
BA+555
90
SBA+WP
RD(0)
P
L
Set
3
555
AA
2AA
55
555
78
Status (8)
4
555
AA
2AA
55
BA+555
58
SA
RD(1)
D
Write
4
555
AA
2AA
55
555
48
SA
X1
Erase
4
555
AA
2AA
55
555
48
SA
X0
Status
4
555
AA
2AA
55
BA+555
58
SA
RD(0)
P
P
Locking Bit Program
(8, 9)
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD(0)
P
P
Locking Bit Program
(8, 9)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD(0)
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