參數(shù)資料
型號(hào)： AM29BDS64HE8VKI
廠商： Spansion Inc.
英文描述： 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 128或64兆位（8米或4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫，突發(fā)模式閃存
文件頁數(shù)： 40/89頁
文件大?。?/td> 913K
代理商： AM29BDS64HE8VKI
38
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A T A S H E E T
mands are valid. To exit the unlock bypass mode, the
system must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the ACC input. When the system asserts V
HH
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
ACC input to accelerate the operation.
Figure 4, “Program Operation,” on page 38
illustrates
the algorithm for the program operation. Refer to the
Erase/Program Operations table in the AC Character-
istics section for parameters, and
Figure 34, “Asyn-
chronous Program Operation Timings: AVD# Latched
Addresses,” on page 70
and
Figure 36, “Synchronous
Program Operation Timings: WE# Latched Addresses,”
on page 72
for timing diagrams.
Figure 4.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
Table 20,
“Memory Array Command Definitions,” on page 46
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete, that
bank returns to the read mode and addresses are no
longer latched. The system can determine the status of
the erase operation by using DQ7 or DQ6/DQ2. Refer
to the
“Write Operation Status” section on page 48
for
information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a
hardware reset
immediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading array
data, to ensure data integrity.
The host system may also initiate the chip erase
command sequence while the device is in the unlock
bypass mode. The command sequence is two cycles
cycles in length instead of six cycles. See
Table 20,
“Memory Array Command Definitions,” on page 46
for
details on the unlock bypass command sequences.
Figure 5, “Erase Operation,” on page 40
illustrates the
algorithm for the erase operation. Refer to the
Erase/Program Operations table in the AC Character-
istics section for parameters and timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command.
Table 20, “Memory Array
Command Definitions,” on page 46
shows the address
and data requirements for the sector erase command
sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
After the command sequence is written, a sector erase
time-out of no less than t
SEA
occurs. During the
time-out period, additional sector addresses and sector
erase commands may be written. Loading the sector
erase buffer may be done in any sequence, and the
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table 20 for program command sequence.
相關(guān)PDF資料
PDF描述
AM29BDS64HE8VMI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HE9VFI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HE9VKI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HE9VMI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS320GTD4VMI 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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