參數(shù)資料
型號(hào)： AM29BDS64HD9VFI
廠商： Spansion Inc.
英文描述： 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 128或64兆位（8米或4個(gè)M x 16位）的CMOS 1.8伏，只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 48/89頁(yè)
文件大?。?/td> 913K
代理商： AM29BDS64HD9VFI
46
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A T A S H E E T
Command Definitions
Table 20.
Memory Array Command Definitions
* For actual hexadecimal data values, refer to the note number indicated.
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch
on the rising edge of the AVD# pulse or active edge of CLK which ever
comes first.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
Notes:
1.
See Table 1 for description of bus operations.
2.
All values are in hexadecimal.
3.
Shaded cells indicate read cycles. All others are write cycles.
4.
Data bits DQ15–DQ8 are don’t care in command sequences, except
for RD and PD.
5.
Unless otherwise noted, address bits Amax–A12 are don’t cares.
6.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state. The
system must write the reset command to return the device to
reading array data.
7.
No unlock or command cycles required when bank is reading array
data.
8.
The Reset command is required to return to reading array data (or to
the erase-suspend-read mode if previously in Erase Suspend) when
a bank is in the autoselect mode, or if DQ5 goes high (while the
bank is providing status information) or performing sector
lock/unlock.
9.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
10. BDS128H: 2218h; BDS640H: 221Eh.
11. BDS128H: 2200h; BDS640H: 2201h
12. The data is 0000h for an unlocked sector and 0001h for a locked
sector
SA = Address of the sector to be verified (in autoselect mode) or erased.
Address bits Amax–A12 uniquely select any sector.
BA = Address of the bank (BDS128H: A22–A20; BDS640H: A21–A19) for
which command is being written.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register address bits A19–A12.
13. DQ15–DQ8 = 0, DQ7: Factory Lock Bit (1 = Locked, 0 = Not
Locked), DQ6: Customer Lock Bit (1 = Locked, 0 = Not Locked),
DQ5: Handshake Bit (1 = Reduced wait-state Handshake, 0 =
Standard Handshake), DQ4–DQ0 = 0
14. The Unlock Bypass command sequence is required prior to this
command sequence.
15. The Unlock Bypass Reset command is required to return to reading
array data when the bank is in the unlock bypass mode.
16. The system may read and program in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The Erase
Suspend command is valid only during a sector erase operation,
and requires the bank address.
17. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
18. See “Set Configuration Register Command Sequence” for details.
This command is unavailable in Unlock Bypass mode.
19. Command is valid when device is ready to read array data or when
device is in autoselect mode.
20. The Unlock Bypass Reset command is required to exit this mode
before sending any other commands to the device. The only
commands that are allowed in the Unlock Bypass mode are the
Entry and exit (Reset), Program, Erase, Sector Erase and CFI.
Command Sequence
(Notes)
C
Bus Cycles (Notes 1–6)
First
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Asynchronous Read (7)
1
RA
RD
Reset (8)
1
XXX
F0
A
Manufacturer ID
4
555
AA
2AA
55
BA+555
90
BA+X00
0001
Device ID (9, 10)*
6
555
AA
2AA
55
BA+555
90
BA+X01
227E
BA+X0E
(10)*
BA+X0F
(11)*
Sector Lock Verify (12)*
4
555
AA
2AA
55
SA+555
90
SA+X02
(12)*
Indicator Bits (13)*
4
555
AA
2AA
55
BA+555
90
BA+X03
(13)*
Program
4
555
AA
2AA
55
555
A0
PA
Data
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
U
Entry
3
555
AA
2AA
55
555
20
Program (14, 15)
2
XX
A0
PA
PD
Sector Erase (14, 15)
2
XX
80
SA
30
Erase (14, 15)
2
XX
80
XXX
10
CFI (14, 15)
1
XX
98
Reset (20)
2
XX
90
XXX
00
Erase Suspend (16)
1
BA
B0
Erase Resume (17)
1
BA
30
Set Configuration Register (18)
3
555
AA
2AA
55
(CR)555
C0
CFI Query (19)
1
55
98
相關(guān)PDF資料
PDF描述
AM29BDS64HD9VKI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HD9VMI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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AM29BDS64HE8VKI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
AM29BDS64HE8VMI 128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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