參數(shù)資料
型號(hào)： AM29BDS643DT9AWLI
廠商： ADVANCED MICRO DEVICES INC
元件分類： PROM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA48
封裝： 11 X 10 MM, 0.50 MM PITCH, FBGA-48
文件頁(yè)數(shù)： 19/46頁(yè)
文件大?。?/td> 693K
代理商： AM29BDS643DT9AWLI
Am29BDS643D
19
P R E L I M I N A R Y
program command sequence. The unlock bypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. That
bank then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip
erase and sector erase sequences in the unlock
bypass mode. The erase command sequences are four
cycles in length instead of six cycles. Table 4 shows the
requirements for the unlock bypass command
sequences.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle
need only contain the data 00h. The bank then returns
to the read mode.
The device offers accelerated program operations
through the V
PP
input. When the system asserts V
PP
on this input, the device automatically enters the
Unlock Bypass mode. The system may then write the
two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
V
PP
input to accelerate the operation. Note that sectors
must be unlocked using the Sector Lock/Unlock
command sequence prior to raising V
PP
to V
ID
.
Figure 1 illustrates the algorithm for the program oper-
ation. Refer to the Erase/Program Operations table in
the AC Characteristics section for parameters, and
Figure 13 for timing diagrams.
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 4 shows
the address and data requirements for the chip erase
command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7 or DQ6/DQ2.
Refer to the Write Operation Status section for infor-
mation on these status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
Note:
See Table 4 for program command sequence.
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