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參數(shù)資料
| 型號： | AM29BDS640GTD3WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁數(shù)： | 49/65頁 |
| 文件大?。?/td> | 899K |
| 代理商： | AM29BDS640GTD3WSI |
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48
Am29BDS640G
October 31, 2002
A D V A N C E I N F O R M A T I O N
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the
first of either the rising edge of AVD# or the active edge of CLK.
3. See the “Erase and Programming Performance” section for more information.
4. Does not include the preprogramming time.
Parameter
Description
All Speed
Options
Unit
JEDEC
Standard
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
ns
t
AVWL
t
AS
Address Setup Time
(Note 2)
Synchronous
Min
5
ns
Asynchronous
0
t
WLAX
t
AH
Address Hold Time
(Note 2)
Synchronous
Min
7
ns
Asynchronous
45
t
ACS
t
ACH
t
DS
t
DH
t
GHWL
t
CAS
t
CH
t
WP
t
WPH
t
SR/W
t
WHWH1
t
WHWH1
Address Setup Time to CLK (Note 2)
Min
5
ns
Address Hold Time to CLK (Note 2)
Min
7
ns
t
DVWH
t
WHDX
t
GHWL
Data Setup Time
Min
45
ns
Data Hold Time
Min
0
ns
Read Recovery Time Before Write
Min
0
ns
CE# Setup Time to AVD#
Min
0
ns
t
WHEH
t
WLWH
t
WHWL
CE# Hold Time
Min
0
ns
Write Pulse Width
Min
50
ns
Write Pulse Width High
Min
30
ns
Latency Between Read and Write Operations
Min
0
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 3)
Typ
8
μs
Accelerated Programming Operation (Note 3)
Typ
2.5
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Notes 3, 4)
Typ
0.2
sec
Chip Erase Operation (Notes 3, 4)
26.8
t
VID
t
VIDS
t
VCS
t
CSW1
t
CSW2
t
CHW
t
CS
t
AVSW
t
AVHW
t
AVHC
t
AVDP
V
ACC
Rise and Fall Time
V
ACC
Setup Time (During Accelerated Programming)
V
CC
Setup Time
Clock Setup Time to WE# (Asynchronous)
Min
500
ns
Min
1
μs
Min
50
μs
Min
5
ns
Clock Setup Time to WE# (Synchronous)
Min
1
ns
Clock Hold Time from WE#
Max
1
ns
t
ELWL
CE# Setup Time to WE#
Min
0
ns
AVD# Setup Time to WE#
Min
5
ns
AVD# Hold Time to WE#
Min
5
ns
AVD# Hold Time to CLK
Min
5
ns
AVD# Low Time
Min
12
ns
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