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參數(shù)資料
| 型號(hào)： | AM29BDS640GTC3WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁(yè)數(shù)： | 51/77頁(yè) |
| 文件大小： | 1581K |
| 代理商： | AM29BDS640GTC3WSI |
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May 9, 2006 25903C2
Am29BDS640G
53
Data
Sheet
AC Characteristics
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed
from two cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state
handshaking under a CLK synchronous burst mode.
Figure 16. Reduced Wait-State Handshaking Burst
Mode Read Starting at an Even Address
Da
Da + 1
Da + n
OE#
DQ15-DQ0
A21-A0
Aa
AVD#
RDY
CLK
CE#
tCAS
tAAS
tAVC
tAVD
tAAH
tOE
tRACC
tOEZ
tCEZ
tIACC
tBDH
7 cycles for initial access shown.
Hi-Z
12
3
4
56
7
tRDYS
tBACC
tACC
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