參數(shù)資料
型號(hào): AM29BDS640GBC9WSI
廠商: SPANSION LLC
元件分類: PROM
英文描述: 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述: 4M X 16 FLASH 1.8V PROM, 20 ns, PBGA80
封裝: 11 X 12 MM, 0.80 MM PITCH, FBGA-80
文件頁(yè)數(shù): 29/77頁(yè)
文件大?。?/td> 1581K
代理商: AM29BDS640GBC9WSI
May 9, 2006 25903C2
Am29BDS640G
33
Data
Sheet
in the standard program command sequence, resulting in faster total program-
ming time. The host system may also initiate the chip erase and sector erase
sequences in the unlock bypass mode. The erase command sequences are four
cycles in length instead of six cycles. Table 13, “Command Definitions,” on
page 37 shows the requirements for the unlock bypass command sequences.
During the unlock bypass mode, only the Unlock Bypass Program, Unlock Bypass
Sector Erase, Unlock Bypass Chip Erase, and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle un-
lock bypass reset command sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need only contain the data 00h. The
bank then returns to the read mode.
The device offers accelerated program operations through the ACC input. When
the system asserts VID on this input, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle Unlock Bypass program
command sequence. The device uses the higher voltage on the ACC input to ac-
celerate the operation.
Figure 2 illustrates the algorithm for the program operation. Refer to the Erase/
Program Operations table in the AC Characteristics section for parameters, and
diagrams.
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector erase timer.
Figure 2. Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
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