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參數(shù)資料
| 型號(hào)： | AM29BDS323DT11AWKI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 110 ns, PBGA47 |
| 封裝： | 7 X 10 MM, 0.50 MM PITCH, FBGA-47 |
| 文件頁(yè)數(shù)： | 37/44頁(yè) |
| 文件大小： | 746K |
| 代理商： | AM29BDS323DT11AWKI |
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Am29BDS323D
37
P R E L I M I N A R Y
AC CHARACTERISTICS
Figure 18.
Initial Access with Power Saving (PS) Function and Address Boundary Latency
Figure 19.
Initial Access with Address Boundary Latency
CLK
AVD#
High-Z
High-Z
High-Z
RDY
High-Z
A/DQ0:
A/DQ15
PS
OE#
PS1
PS2
device is programmable from 4 to 7 total cycles
during initial access (here, programmable wait state
function is set to 02h; 6 cycles total)
PS high if data is inverted,
low if data is not inverted
1 additional
wait state if
address is
at boundary
1 additional
wait state to
indicate PS
is enabled
AVD# low with clock
present enables
burst read mode
Address
A16:A21
PS
boundary
latency
Address
D1
D2
D0
CLK
AVD#
High-Z
High-Z
RDY
High-Z
A/DQ0:
A/DQ15
OE#
device is programmable from 4 to 7 total cycles
during initial access (here, programmable wait state
function is set to 02h; 6 cycles total)
1 additional
wait state if
address is
at boundary
AVD# low with clock
present enables
burst read mode
Address
A16:A21
boundary
latency
Address
D1
D2
D0
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