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參數(shù)資料
| 型號： | AM29BDS320GTD3VMI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA64 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 19/74頁 |
| 文件大小： | 701K |
| 代理商： | AM29BDS320GTD3VMI |
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October 1, 2003 27243B1
Am29BDS320G
17
P r e l i m i n a r y
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
SS
± 0.2 V, the device draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
± 0.2 V, the standby current will be greater.
RESET# may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase operation, the device requires
a time of t
READY
(during Embedded Algorithms) before the device is ready to read
data again. If RESET# is asserted when a program or erase operation is not ex-
ecuting, the reset operation is completed within a time of t
READY
(not during
Embedded Algorithms). The system can read data t
RH
after RESET# returns to
V
IH
.
Refer to the AC Characteristics tables for RESET# parameters and to
Figure 20,
“Reset Timings,” on page 56
for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The outputs are
placed in the high impedance state.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing
provides data protection against inadvertent writes (refer to
Table 14, “Command
Definitions,” on page 36
for command definitions).
The device offers two types of data protection at the sector level:
The sector lock/unlock command sequence disables or re-enables both pro-
gram and erase operations in any sector.
When WP# is at V
IL
, sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top
boot) are locked.
When ACC is at V
IL
, all sectors are locked.
The following hardware data protection measures prevent accidental erasure or
programming, which might otherwise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or from system noise.
W rite Protect ( W P# )
The Write Protect (WP#) input provides a hardware method of protecting data
without using V
ID
.
If the system asserts V
IL
on the WP# pin, the device disables program and erase
functions in sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot).
If the system asserts V
IH
on the WP# pin, the device reverts to whether the two
outermost 8K Byte boot sectors were last set to be protected or unprotected.
Note that the WP# pin must not be left floating or unconnected; inconsistent be-
havior of the device may result.
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This pro-
tects data during V
CC
power-up and power-down. The command register and all
internal program/erase circuits are disabled, and the device resets to reading
array data. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The sys-
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