參數(shù)資料
型號： AM29BDS320GTC8VMI
廠商： SPANSION LLC
元件分類： DRAM
英文描述： 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 2M X 16 FLASH 1.8V PROM, 90 ns, PBGA64
封裝： 8 X 9 MM, 0.80 MM PITCH, FBGA-64
文件頁數(shù)： 6/74頁
文件大?。?/td> 701K
代理商： AM29BDS320GTC8VMI
4
Am29BDS320G
27243B1 October 1, 2003
P r e l i m i n a r y
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram of Simultaneous
Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .9
Special Handling Instructions for FBGA Package ..........................9
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 10
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 11
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 12
Table 1. Device Bus Operations ..........................................12
Enhanced VersatileIO (V
IO
) Control ............................................12
Requirements for Asynchronous Read
Operation (Non-Burst) ........................................................................12
Requirements for Synchronous (Burst) Read Operation .........13
8-, 16-, and 32-Word Linear Burst with Wrap Around .............14
Table 2. Burst Address Groups ............................................14
Burst Mode Configuration Register .................................................14
Reduced Wait-State Handshaking Option .....................................14
Simultaneous Read/Write Operations with Zero Latency .......15
Writing Commands/Command Sequences ...................................15
Accelerated Program Operation ......................................................15
Autoselect Functions ............................................................................16
Standby Mode .........................................................................................16
Automatic Sleep Mode .........................................................................16
RESET#: Hardware Reset Input ........................................................16
Output Disable Mode ...........................................................................17
Hardware Data Protection .................................................................17
Write Protect (WP#) ...........................................................................17
Low V
CC
Write Inhibit ........................................................................17
Write Pulse “Glitch” Protection .......................................................18
Logical Inhibit ..........................................................................................18
Power-Up Write Inhibit ......................................................................18
V
CC
and V
IO
Power-up And Power-down Sequencing .............18
Common Flash Memory Interface (CFI) . . . . . . .18
Table 3. CFI Query Identification String ...............................19
System Interface String..................................................... 19
Table 5. Device Geometry Definition......................................... 20
Table 6. Primary Vendor-Specific Extended Query................. 21
Table 7. Sector Address Table...................................................... 22
Command Definitions . . . . . . . . . . . . . . . . . . . . . .25
Reading Array Data .............................................................................25
Set Burst Mode Configuration Register Command Sequence 25
Figure 1. Synchronous/Asynchronous State Diagram ............. 26
Read Mode Setting ...............................................................................26
Programmable Wait State Configuration ......................................26
Table 8. Programmable Wait State Settings ..........................27
Reduced Wait-State Handshaking Option ....................................27
Table 9. Initial Access Cycles vs. Frequency ..........................27
Standard Handshaking Operation ...................................................28
Table 10. Wait States for Standard Handshaking ...................28
Burst Read Mode Configuration ......................................................28
Table 11. Burst Read Mode Settings ....................................28
Burst Active Clock Edge Configuration .........................................28
RDY Configuration ..............................................................................29
Configuration Register ........................................................................29
Table 12. Burst Mode Configuration Register ........................ 29
Sector Lock/Unlock Command Sequence ....................................29
Reset Command ...................................................................................30
Autoselect Command Sequence .....................................................30
Table 13. Device IDs ......................................................... 31
Program Command Sequence ............................................................31
Unlock Bypass Command Sequence ................................................31
Figure 2. Erase Operation.................................................. 32
Chip Erase Command Sequence ......................................................32
Sector Erase Command Sequence ...................................................33
Erase Suspend/Erase Resume Commands .....................................34
Figure 3. Program Operation.............................................. 35
Command Definitions ..........................................................................36
Table 14. Command Definitions ......................................... 36
Write Operation Status . . . . . . . . . . . . . . . . . . . . 37
DQ7: Data# Polling ..............................................................................37
Figure 4. Data# Polling Algorithm....................................... 38
RDY: Ready .............................................................................................38
DQ6: Toggle Bit I ..................................................................................39
Figure 5. Toggle Bit Algorithm............................................ 40
DQ2: Toggle Bit II ................................................................................40
Table 15. DQ6 and DQ2 Indications .................................... 41
Reading Toggle Bits DQ6/DQ2 ........................................................41
DQ5: Exceeded Timing Limits ...........................................................41
DQ3: Sector Erase Timer ..................................................................42
Table 16. Write Operation Status ........................................ 42
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 43
Figure 6. Maximum Negative Overshoot Waveform ............... 43
Figure 7. Maximum Positive Overshoot Waveform................. 43
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . 43
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44
CMOS Compatible ..............................................................................44
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 8. Test Setup ......................................................... 45
Table 17. Test Specifications .............................................. 45
Key to Switching Waveforms . . . . . . . . . . . . . . . . 45
Figure 9. Input Waveforms and Measurement Levels............. 45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 10. V
CC
and V
IO
Power-up Diagram........................... 46
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47
Synchronous/Burst Read .....................................................................47
Figure 11. CLK Synchronous Burst Mode Read
(rising active CLK)............................................................ 48
Figure 12. CLK Synchronous Burst Mode Read
(Falling Active Clock) ........................................................ 49
Figure 13. Synchronous Burst Mode Read............................ 50
Figure 14. 8-word Linear Burst with Wrap Around................. 50
Figure 15. Burst with RDY Set One Cycle Before Data............ 51
Figure 16. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Even Address .............................................. 52
Figure 17. Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address................................................ 53
Asynchronous Read ..............................................................................54
Figure 18. Asynchronous Mode Read with Latched Addresses . 54
Figure 19. Asynchronous Mode Read................................... 55
Figure 20. Reset Timings................................................... 56
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