參數(shù)資料
型號： AM29BDD160GB20DKI
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存
文件頁數(shù)： 37/79頁
文件大?。?/td> 1368K
代理商： AM29BDD160GB20DKI
June 7, 2006
Am29BDD160G
35
The Re
s
et comm
a
nd doe
s
not d
isab
le the
S
ec
Si
s
ec-
tor
i
f
i
t
is
en
ab
led
.
Th
is
f
u
nct
i
on
is
only
a
ccompl
is
hed
b
y
issui
ng the
S
ec
Si
S
ector Ex
i
t comm
a
nd
.
Auto
s
elect Command
Fl
as
h memor
i
e
s
a
re
i
ntended for
us
e
i
n
a
ppl
i
c
a
t
i
on
s
where the loc
a
l CPU
a
lter
s
memory content
s.
A
s
su
ch,
m
a
n
u
f
a
ct
u
rer
a
nd dev
i
ce code
s
m
us
t
b
e
a
cce
ssib
le
wh
i
le the dev
i
ce re
si
de
s
i
n the t
a
rget
s
y
s
tem
.
PROM
progr
a
mmer
s
typ
i
c
a
lly
a
cce
ss
the
si
gn
a
t
u
re code
s
b
y
r
aisi
ng A
9
to V
ID
.
However, m
u
lt
i
plex
i
ng h
i
gh volt
a
ge
onto the
a
ddre
ss
l
i
ne
s
is
not gener
a
lly de
si
red
s
y
s
tem
de
si
gn pr
a
ct
i
ce
.
The Am2
9
BDD160 cont
ai
n
s
a
n A
u
to
s
elect Comm
a
nd
oper
a
t
i
on to
su
pplement tr
a
d
i
t
i
on
a
l PROM progr
a
m-
m
i
ng methodology
.
The oper
a
t
i
on
is
i
n
i
t
ia
ted
b
y wr
i
t
i
ng
the A
u
to
s
elect comm
a
nd
s
e
qu
ence
i
nto the comm
a
nd
reg
is
ter
.
The
ba
nk
a
ddre
ss
(BA)
is
l
a
tched d
u
r
i
ng the
au
to
s
elect comm
a
nd
s
e
qu
ence wr
i
te oper
a
t
i
on to d
is
-
t
i
ng
uis
h wh
i
ch
ba
nk the A
u
to
s
elect comm
a
nd refer-
ence
s.
Re
a
d
i
ng the other
ba
nk
a
fter the A
u
to
s
elect
comm
a
nd
is
wr
i
tten re
su
lt
s
i
n re
a
d
i
ng
a
rr
a
y d
a
t
a
from
the other
ba
nk
a
nd the
s
pec
i
f
i
ed
a
ddre
ss.
Follow
i
ng
the comm
a
nd wr
i
te,
a
re
a
d cycle from
a
ddre
ss
(BA)XX00h retr
i
eve
s
the m
a
n
u
f
a
ct
u
rer code of
(BA)XX01h
.
Three
s
e
qu
ent
ia
l re
a
d cycle
s
a
t
a
d-
dre
ss
e
s
(BA) XX01h, (BA) XX0Eh,
a
nd (BA) XX0Fh
re
a
d the three-
b
yte dev
i
ce ID (
s
ee T
ab
le
s
1
9
a
nd 20)
.
All m
a
n
u
f
a
ct
u
rer
a
nd dev
i
ce code
s
exh
ibi
t odd p
a
r
i
ty
w
i
th the M
S
B of the lower
b
yte (DQ7) def
i
ned
as
the
p
a
r
i
ty
bi
t
.
(The A
u
to
s
elect Comm
a
nd re
qui
re
s
the
us
er to exe-
c
u
te the Re
a
d/Re
s
et comm
a
nd to ret
u
rn the dev
i
ce
ba
ck to re
a
d
i
ng the
a
rr
a
y content
s.
)
Pro
g
ram Command
S
equence
Progr
a
mm
i
ng
is
a
fo
u
r-
bus
-cycle oper
a
t
i
on
.
The pro-
gr
a
m comm
a
nd
s
e
qu
ence
is
i
n
i
t
ia
ted
b
y wr
i
t
i
ng two
u
nlock wr
i
te cycle
s
, followed
b
y the progr
a
m
s
et-
u
p
comm
a
nd
.
The progr
a
m
a
ddre
ss
a
nd d
a
t
a
a
re wr
i
tten
next, wh
i
ch
i
n t
u
rn
i
n
i
t
ia
te the Em
b
edded Progr
a
m
a
l-
gor
i
thm
.
The
s
y
s
tem
is
not
re
qui
red to prov
i
de f
u
rther
control
s
or t
i
m
i
ng
s.
The dev
i
ce
au
tom
a
t
i
c
a
lly gener-
a
te
s
the progr
a
m p
u
l
s
e
s
a
nd ver
i
f
i
e
s
the progr
a
mmed
cell m
a
rg
i
n
.
T
ab
le
s
1
8
a
nd 20
s
how
s
the
a
ddre
ss
a
nd
d
a
t
a
re
qui
rement
s
for the progr
a
m comm
a
nd
s
e-
qu
ence
.
D
u
r
i
ng the Em
b
edded Progr
a
m
a
lgor
i
thm, the
s
y
s
tem
c
a
n determ
i
ne the
s
t
a
t
us
of the progr
a
m oper
a
t
i
on
b
y
usi
ng DQ7, DQ6, or RY/BY#
.
(
S
ee
Wr
i
te Oper
a
t
i
on
S
t
a
t
us
for
i
nform
a
t
i
on on the
s
e
s
t
a
t
us
bi
t
s.
) When the
Em
b
edded Progr
a
m
a
lgor
i
thm
is
complete, the dev
i
ce
ret
u
rn
s
to re
a
d
i
ng
a
rr
a
y d
a
t
a
a
nd
a
ddre
ss
e
s
a
re no
longer l
a
tched
.
Note th
a
t
a
n
a
ddre
ss
ch
a
nge
is
re-
qui
red to
b
eg
i
n re
a
d v
a
l
i
d
a
rr
a
y d
a
t
a.
Except for Progr
a
m
Sus
pend,
a
ny comm
a
nd
s
wr
i
tten
to the dev
i
ce d
u
r
i
ng the Em
b
edded Progr
a
m Algor
i
thm
a
re
i
gnored
.
Note th
a
t
a
hardware re
s
et
i
mmed
ia
tely
term
i
n
a
te
s
the progr
a
mm
i
ng oper
a
t
i
on
.
The comm
a
nd
s
e
qu
ence
s
ho
u
ld
b
e re
i
n
i
t
ia
ted once th
a
t
ba
nk h
as
re-
t
u
rned to re
a
d
i
ng
a
rr
a
y d
a
t
a
, to en
su
re d
a
t
a
i
ntegr
i
ty
.
Progr
a
mm
i
ng
is
a
llowed
i
n
a
ny
s
e
qu
ence
a
nd
a
cro
ss
s
ector
b
o
u
nd
a
r
i
e
s.
A b
i
t cannot be pro
g
rammed
from a “0” back to a “1”
.
Attempt
i
ng to do
s
o m
a
y
h
a
lt the oper
a
t
i
on
a
nd
s
et DQ5 to “1,” or c
aus
e the
D
a
t
a
# Poll
i
ng
a
lgor
i
thm to
i
nd
i
c
a
te the oper
a
t
i
on w
as
su
cce
ss
f
u
l
.
However,
a
su
cceed
i
ng re
a
d w
i
ll
s
how th
a
t
the d
a
t
a
is
s
t
i
ll “0”
.
Only er
as
e oper
a
t
i
on
s
c
a
n convert
a
“0” to
a
“1”
.
Accelerated Pro
g
ram Command
The Acceler
a
ted Ch
i
p Progr
a
m mode
is
de
si
gned to
i
mprove the Word or Do
ub
le Word progr
a
mm
i
ng
s
peed
.
Improv
i
ng the progr
a
mm
i
ng
s
peed
is
a
ccom-
pl
is
hed
b
y
usi
ng the ACC p
i
n to
su
pply
b
oth the word-
l
i
ne volt
a
ge
a
nd the
bi
tl
i
ne c
u
rrent
i
n
s
te
a
d of
usi
ng the
V
PP
p
u
mp
a
nd dr
ai
n p
u
mp, wh
i
ch
is
l
i
m
i
ted to 2
.
5 mA
.
Bec
aus
e the extern
a
l ACC p
i
n
is
c
a
p
ab
le of
su
pply
i
ng
si
gn
i
f
i
c
a
ntly l
a
rge
a
mo
u
nt
s
of c
u
rrent comp
a
red to the
dr
ai
n p
u
mp,
a
ll
3
2
bi
t
s
a
re
a
v
ai
l
ab
le for progr
a
mm
i
ng
w
i
th
a
si
ngle progr
a
mm
i
ng p
u
l
s
e
.
Th
is
is
a
n enormo
us
i
mprovement over the
s
t
a
nd
a
rd 5-
bi
t progr
a
mm
i
ng
.
If
the
us
er
is
ab
le to
su
pply
a
n extern
a
l power
su
pply
a
nd connect
i
t to the ACC p
i
n,
si
gn
i
f
i
c
a
nt t
i
me
sa
v
i
ng
s
a
re re
a
l
i
zed
.
In order to enter the Acceler
a
ted Progr
a
m mode, the
ACC p
i
n m
us
t f
i
r
s
t
b
e t
a
ken to V
HH
(12 V ± 0
.
5 V)
a
nd
followed
b
y the one-cycle comm
a
nd w
i
th the progr
a
m
a
ddre
ss
a
nd d
a
t
a
to follow
.
The Acceler
a
ted Ch
i
p Pro-
gr
a
m comm
a
nd
is
only exec
u
ted when the dev
i
ce
is
i
n
Unlock Byp
ass
mode
a
nd d
u
r
i
ng norm
a
l re
a
d/re
s
et
oper
a
t
i
ng mode
.
In th
is
mode, the wr
i
te protect
i
on f
u
nct
i
on
is
b
yp
ass
ed
u
nle
ss
the PPB Lock B
i
t = 1
.
The Acceler
a
ted Progr
a
m comm
a
nd
is
not perm
i
tted
i
f
the
S
ec
Si
s
ector
is
en
ab
led
.
Unlock Bypa
ss
Command
S
equence
The
u
nlock
b
yp
ass
fe
a
t
u
re
a
llow
s
the
s
y
s
tem to pro-
gr
a
m word
s
to the dev
i
ce f
as
ter th
a
n
usi
ng the
s
t
a
n-
d
a
rd progr
a
m comm
a
nd
s
e
qu
ence
.
The
u
nlock
b
yp
ass
comm
a
nd
s
e
qu
ence
is
i
n
i
t
ia
ted
b
y f
i
r
s
t wr
i
t
i
ng two
u
n-
lock cycle
s.
Th
is
is
followed
b
y
a
th
i
rd wr
i
te cycle con-
t
ai
n
i
ng the
u
nlock
b
yp
ass
comm
a
nd, 20h
.
The dev
i
ce
then enter
s
the
u
nlock
b
yp
ass
mode
.
A two-cycle
u
n-
lock
b
yp
ass
progr
a
m comm
a
nd
s
e
qu
ence
is
a
ll th
a
t
is
re
qui
red to progr
a
m
i
n th
is
mode
.
The f
i
r
s
t cycle
i
n th
is
s
e
qu
ence cont
ai
n
s
the
u
nlock
b
yp
ass
progr
a
m com-
m
a
nd, A0h
;
the
s
econd cycle cont
ai
n
s
the progr
a
m
a
ddre
ss
a
nd d
a
t
a.
Add
i
t
i
on
a
l d
a
t
a
is
progr
a
mmed
i
n
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