參數(shù)資料
型號： AM29BDD160GB20DKF
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存
文件頁數(shù)： 23/79頁
文件大?。?/td> 1368K
代理商： AM29BDD160GB20DKF
June 7, 2006
Am29BDD160G
21
Bur
s
t Acce
ss
T
i
m
i
n
g
Control
In
a
dd
i
t
i
on to the IND/WAIT#
si
gn
a
l control,
bu
r
s
t con-
trol
s
ex
is
t
i
n the Control Reg
is
ter for
i
n
i
t
ia
l
a
cce
ss
de-
l
a
y, del
i
very of d
a
t
a
on the CLK edge,
a
nd the length
of t
i
me d
a
t
a
is
held
.
In
i
t
i
al Bur
s
t Acce
ss
Delay Control
The Am2
9
BDD160 cont
ai
n
s
opt
i
on
s
for
i
n
i
t
ia
l
a
cce
ss
del
a
y of
a
bu
r
s
t
a
cce
ss.
The
i
n
i
t
ia
l
a
cce
ss
del
a
y h
as
no effect on
as
ynchrono
us
re
a
d oper
a
t
i
on
s.
B
u
r
s
t In
i
t
ia
l Acce
ss
Del
a
y
is
def
i
ned
as
the n
u
m
b
er of
clock cycle
s
th
a
t m
us
t el
a
p
s
e from the f
i
r
s
t v
a
l
i
d clock
edge
a
fter ADV#
ass
ert
i
on (or the r
isi
ng edge of
ADV#)
u
nt
i
l the f
i
r
s
t v
a
l
i
d CLK edge when the d
a
t
a
is
v
a
l
i
d
.
The
bu
r
s
t
a
cce
ss
is
i
n
i
t
ia
ted
a
nd the
a
ddre
ss
is
l
a
tched on the f
i
r
s
t r
isi
ng CLK edge when ADV#
is
a
c-
t
i
ve or
u
pon
a
r
isi
ng ADV# edge, wh
i
chever come
s
f
i
r
s
t
.
(
S
ee T
ab
le
8
de
s
cr
ib
e
s
the
i
n
i
t
ia
l
a
cce
ss
del
a
y
conf
i
g
u
r
a
t
i
on
s.
) If the Clock Conf
i
g
u
r
a
t
i
on
bi
t
i
n the
Control Reg
is
ter
is
s
et to f
a
ll
i
ng edge (CR6 = 0), the
def
i
n
i
t
i
on rem
ai
n
s
the
sa
me for the
i
n
i
t
ia
l del
a
y
s
ett
i
ng
w
i
th the except
i
on th
a
t d
a
t
a
is
v
a
l
i
d
a
fter the f
a
ll
i
ng
edge
.
Table
8.
Bur
s
t In
i
t
i
al Acce
ss
Delay
F
ig
ure
3.
In
i
t
i
al Bur
s
t Delay Control
Notes:
1
.
B
u
r
s
t
a
cce
ss
s
t
a
rt
s
w
i
th
a
r
isi
ng CLK edge
a
nd when ADV#
is
a
ct
i
ve
.
2
.
Conf
i
g
u
r
a
t
i
on
s
reg
is
ter 6
is
s
et to 1 (CR6 = 1)
.
B
u
r
s
t
s
t
a
rt
s
a
nd d
a
t
a
o
u
tp
u
t
s
on the r
isi
ng CLK edge
.
3
.
CR [13-10] = 1 or three clock cycle
s
4
.
CR [13-10] = 2 or fo
u
r clock cycle
s
5
.
CR [13-10] = 3 or F
i
ve clock cycle
s
CR1
3
CR12
CR11
CR10
In
i
t
i
al Bur
s
t Acce
ss
(CLK cycle
s
)
54D,
64C, 65A
0
0
0
0
2
0
0
0
1
3
0
0
1
0
4
0
0
1
1
5
0
1
0
0
6
0
1
0
1
7
0
1
1
0
8
0
1
1
1
9
CLK
ADV#
A1
8
-
A0
DQ
3
1
-
DQ0
3
DQ
3
1
-
DQ0
4
DQ
3
1
-
DQ0
5
V
a
l
i
d Addre
ss
Three CLK Del
a
y
2nd CLK
3
rd CLK
4th CLK
5th CLK
1
s
t CLK
Fo
u
r CLK Del
a
y
Addre
ss
1 L
a
tched
F
i
ve CLK Del
a
y
D0
D1
D2
D
3
D0
D1
D2
D0
D1
D2
D
3
D4
相關(guān)PDF資料
PDF描述
AM29BDD160GB20DKI 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20DKK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20DPBE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20DPBF 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160G 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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