參數(shù)資料
型號: AM29BDD160GB20APBF
廠商: Advanced Micro Devices, Inc.
英文描述: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述: 16兆位(1 M中的x 16-bit/512畝× 32位),2.5伏的CMOS只突發(fā)模式,雙啟動,同步讀/寫閃存
文件頁數(shù): 54/79頁
文件大小: 1368K
代理商: AM29BDD160GB20APBF
52
Am29BDD160G
June 7, 2006
DQ
3
:
S
ector Era
s
e T
i
mer
After wr
i
t
i
ng
a
s
ector er
as
e comm
a
nd
s
e
qu
ence, the
s
y
s
tem m
a
y re
a
d DQ
3
to determ
i
ne whether or not
a
n
er
as
e oper
a
t
i
on h
as
b
eg
u
n
.
(The
s
ector er
as
e t
i
mer
doe
s
not
a
pply to the ch
i
p er
as
e comm
a
nd
.
) If
a
dd
i
t
i
on
a
l
s
ector
s
a
re
s
elected for er
asu
re, the ent
i
re t
i
me-o
u
t
a
l
s
o
a
ppl
i
e
s
a
fter e
a
ch
a
dd
i
t
i
on
a
l
s
ector er
as
e comm
a
nd
.
When the t
i
me-o
u
t
is
complete, DQ
3
s
w
i
tche
s
from “0”
to “1
.
” The
s
y
s
tem m
a
y
i
gnore DQ
3
i
f the
s
y
s
tem c
a
n
g
ua
r
a
ntee th
a
t the t
i
me
b
etween
a
dd
i
t
i
on
a
l
s
ector
er
as
e comm
a
nd
s
w
i
ll
a
lw
a
y
s
b
e le
ss
th
a
n 50
μs.
S
ee
a
l
s
o the
S
ector Er
as
e Comm
a
nd
s
ect
i
on
.
After the
s
ector er
as
e comm
a
nd
s
e
qu
ence
is
wr
i
tten,
the
s
y
s
tem
s
ho
u
ld re
a
d the
s
t
a
t
us
on DQ7 (D
a
t
a
# Poll-
i
ng) or DQ6 (Toggle B
i
t I) to en
su
re the dev
i
ce h
as
a
c-
cepted the comm
a
nd
s
e
qu
ence,
a
nd then re
a
d DQ
3.
If
DQ
3
is
“1”, the
i
ntern
a
lly controlled er
as
e cycle h
as
b
e-
g
u
n
;
a
ll f
u
rther comm
a
nd
s
(other th
a
n Er
as
e
Sus
pend)
a
re
i
gnored
u
nt
i
l the er
as
e oper
a
t
i
on
is
complete
.
If
DQ
3
is
“0”, the dev
i
ce w
i
ll
a
ccept
a
dd
i
t
i
on
a
l
s
ector
er
as
e comm
a
nd
s.
To en
su
re the comm
a
nd h
as
b
een
a
ccepted, the
s
y
s
tem
s
oftw
a
re
s
ho
u
ld check the
s
t
a
t
us
of DQ
3
pr
i
or to
a
nd follow
i
ng e
a
ch
subs
e
qu
ent
s
ector
er
as
e comm
a
nd
.
If DQ
3
is
h
i
gh on the
s
econd
s
t
a
t
us
check, the l
as
t comm
a
nd m
i
ght not h
a
ve
b
een
a
c-
cepted
.
T
ab
le 2
3
s
how
s
the o
u
tp
u
t
s
for DQ
3.
Table 2
3.
Wr
i
te Operat
i
on
S
tatu
s
Notes:
1
.
DQ5
s
w
i
tche
s
to ‘1’ when
a
n Em
b
edded Progr
a
m or Em
b
edded Er
as
e oper
a
t
i
on h
as
exceeded the m
a
x
i
m
u
m t
i
m
i
ng l
i
m
i
t
s.
See
DQ5
:
Exceeded T
i
m
i
ng L
i
m
i
t
s
for more
i
nform
a
t
i
on
.
2
.
DQ7
a
nd DQ2 re
qui
re
a
v
a
l
i
d
a
ddre
ss
when re
a
d
i
ng
s
t
a
t
us
i
nform
a
t
i
on
.
Refer to the
a
ppropr
ia
te
subs
ect
i
on for f
u
rther det
ai
l
s.
Operat
i
on
Em
b
edded Progr
a
m Algor
i
thm
Em
b
edded Er
as
e Algor
i
thm
Re
a
d
i
ng w
i
th
i
n Er
as
e
Sus
pended
S
ector
Re
a
d
i
ng w
i
th
i
n Non-Er
as
e
Sus
pended
S
ector
Er
as
e-
Sus
pend-Progr
a
m
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ
3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
RY/BY#
0
0
S
t
a
nd
a
rd
Mode
Er
as
e
Sus
pend
Mode
1
No toggle
0
N/A
Toggle
1
D
a
t
a
D
a
t
a
D
a
t
a
D
a
t
a
D
a
t
a
1
DQ7#
Toggle
0
N/A
N/A
0
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