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| 型號： | AM29BDD160GB20AKE |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存 |
| 文件頁數(shù)： | 53/79頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB20AKE |
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June 7, 2006
Am29BDD160G
51
the
s
ector
is
a
ct
i
vely er
asi
ng or
is
er
as
e-
sus
pended
.
DQ6,
b
y comp
a
r
is
on,
i
nd
i
c
a
te
s
whether the dev
i
ce
is
a
ct
i
vely er
asi
ng, or
is
i
n Er
as
e
Sus
pend,
bu
t c
a
nnot
d
is
t
i
ng
uis
h wh
i
ch
s
ector
s
a
re
s
elected for er
asu
re
.
Th
us
,
b
oth
s
t
a
t
us
bi
t
s
a
re re
qui
red for
s
ector
a
nd mode
i
nform
a
t
i
on
.
Refer to T
ab
le 2
3
to comp
a
re o
u
tp
u
t
s
for
DQ2
a
nd DQ6
.
F
i
g
u
re 7
s
how
s
the toggle
bi
t
a
lgor
i
thm
i
n flowch
a
rt
form,
a
nd the
s
ect
i
on
Re
a
d
i
ng Toggle B
i
t
s
DQ6/DQ2
expl
ai
n
s
the
a
lgor
i
thm
.
S
ee
a
l
s
o the
DQ6
:
Toggle B
i
t I
subs
ect
i
on
.
F
i
g
u
re 25
s
how
s
the toggle
bi
t t
i
m
i
ng d
ia
-
gr
a
m
.
F
i
g
u
re 25
s
how
s
the d
i
fference
s
b
etween DQ2
a
nd DQ6
i
n gr
a
ph
i
c
a
l form
.
F
i
g
u
re 27
s
how
s
the t
i
m
i
ng
d
ia
gr
a
m for
s
ynchrono
us
DQ2 toggle
bi
t
s
t
a
t
us.
Read
i
n
g
To
gg
le B
i
t
s
DQ6/DQ2
Refer to F
i
g
u
re 25 for the follow
i
ng d
is
c
ussi
on
.
When-
ever the
s
y
s
tem
i
n
i
t
ia
lly
b
eg
i
n
s
re
a
d
i
ng toggle
bi
t
s
t
a
-
t
us
,
i
t m
us
t perform two
i
mmed
ia
tely con
s
ec
u
t
i
ve
re
a
d
s
of DQ7–DQ0 to determ
i
ne whether
a
toggle
bi
t
is
toggl
i
ng
.
Typ
i
c
a
lly, the
s
y
s
tem wo
u
ld note
a
nd
s
tore
the v
a
l
u
e of the toggle
bi
t
a
fter the f
i
r
s
t re
a
d
.
After the
s
econd re
a
d, the
s
y
s
tem wo
u
ld comp
a
re the new
v
a
l
u
e of the toggle
bi
t w
i
th the f
r
s
t
.
If the toggle
bi
t
is
not toggl
i
ng, the dev
i
ce h
as
completed the progr
a
m or
er
as
e oper
a
t
i
on
.
The
s
y
s
tem c
a
n re
a
d
a
rr
a
y d
a
t
a
on
DQ7–DQ0 on the follow
i
ng re
a
d cycle
.
However,
i
f
a
fter the
i
n
i
t
ia
l two
i
mmed
ia
tely con
s
ec
u
t
i
ve
re
a
d cycle
s
, the
s
y
s
tem determ
i
ne
s
th
a
t the toggle
bi
t
is
s
t
i
ll toggl
i
ng, the
s
y
s
tem
a
l
s
o
s
ho
u
ld note whether
the v
a
l
u
e of DQ5
is
h
i
gh (
s
ee the
s
ect
i
on on DQ5)
.
If
i
t
is
, the
s
y
s
tem
s
ho
u
ld then determ
i
ne
a
g
ai
n whether the
toggle
bi
t
is
toggl
i
ng,
si
nce the toggle
bi
t m
a
y h
a
ve
s
topped toggl
i
ng
jus
t
as
DQ5 went h
i
gh
.
If the toggle
bi
t
is
no longer toggl
i
ng, the dev
i
ce h
as
su
cce
ss
f
u
lly com-
pleted the progr
a
m or er
as
e oper
a
t
i
on
.
If
i
t
is
s
t
i
ll tog-
gl
i
ng, the dev
i
ce d
i
d not complete the oper
a
t
i
on
su
cce
ss
f
u
lly,
a
nd the
s
y
s
tem m
us
t wr
i
te the re
s
et com-
m
a
nd to ret
u
rn to re
a
d
i
ng
a
rr
a
y d
a
t
a.
The rem
ai
n
i
ng
s
cen
a
r
i
o
is
th
a
t the
s
y
s
tem
i
n
i
t
ia
lly
determ
i
ne
s
th
a
t the toggle
bi
t
is
toggl
i
ng
a
nd DQ5 h
as
not gone h
i
gh
.
The
s
y
s
tem m
a
y cont
i
n
u
e to mon
i
tor the
toggle
bi
t
a
nd DQ5 thro
u
gh
su
cce
ssi
ve re
a
d cycle
s
,
determ
i
n
i
ng the
s
t
a
t
us
as
de
s
cr
ib
ed
i
n the prev
i
o
us
p
a
r
a
gr
a
ph
.
Altern
a
t
i
vely,
i
t m
a
y choo
s
e to perform
other
s
y
s
tem t
as
k
s.
In th
is
c
as
e, the
s
y
s
tem m
us
t
s
t
a
rt
a
t the
b
eg
i
nn
i
ng of the
a
lgor
i
thm when
i
t ret
u
rn
s
to
determ
i
ne the
s
t
a
t
us
of the oper
a
t
i
on (top of F
i
g
u
re 7)
.
DQ5: Exceeded T
i
m
i
n
g
L
i
m
i
t
s
DQ5
i
nd
i
c
a
te
s
whether the progr
a
m or er
as
e t
i
me h
as
exceeded
a
s
pec
i
f
i
ed
i
ntern
a
l p
u
l
s
e co
u
nt l
i
m
i
t
.
Under
the
s
e cond
i
t
i
on
s
DQ5 prod
u
ce
s
a
“1
.
” Th
is
is
a
f
ai
l
u
re
cond
i
t
i
on th
a
t
i
nd
i
c
a
te
s
the progr
a
m or er
as
e cycle w
as
not
su
cce
ss
f
u
lly completed
.
The DQ5 f
ai
l
u
re cond
i
t
i
on m
a
y
a
ppe
a
r
i
f the
s
y
s
tem
tr
i
e
s
to progr
a
m
a
“1” to
a
loc
a
t
i
on th
a
t
is
prev
i
o
us
ly
progr
a
mmed to “0
.
”
Only an era
s
e operat
i
on can
chan
g
e a “0” back to a “1
.
”
Under th
is
cond
i
t
i
on, the
dev
i
ce h
a
lt
s
the oper
a
t
i
on,
a
nd when the oper
a
t
i
on h
as
exceeded the t
i
m
i
ng l
i
m
i
t
s
, DQ5 prod
u
ce
s
a
“1
.
”
Under
b
oth the
s
e cond
i
t
i
on
s
, the
s
y
s
tem m
us
t
issu
e
the re
s
et comm
a
nd to ret
u
rn the dev
i
ce to re
a
d
i
ng
a
rr
a
y d
a
t
a.
S
TART
No
Ye
s
Ye
s
DQ5 = 1
No
Ye
s
DQ6 = Toggle
No
Re
a
d Byte
(DQ0-DQ7)
Addre
ss
= VA
DQ6 = Toggle
Re
a
d Byte Tw
i
ce
(DQ 0-DQ7)
Adrde
ss
= VA
Re
a
d Byte
(DQ0-DQ7)
Addre
ss
= VA
FAIL
PA
SS
Notes:
1
.
Re
a
d toggle
bi
t w
i
th two
i
mmed
ia
tely con
s
ec
u
t
i
ve re
a
d
s
to determ
i
ne whether or not
i
t
is
toggl
i
ng
.
See text
.
2
.
Recheck toggle
bi
t
b
ec
aus
e
i
t m
a
y
s
top toggl
i
ng
as
DQ5
ch
a
nge
s
to “1”
.
See text
.
F
ig
ure 7
.
To
gg
le B
i
t Al
g
or
i
thm
(Note 1)
(Note
s
1, 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB20AKF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20AKI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20AKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB20APBF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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