參數(shù)資料
型號(hào)： AM29BDD160GB17DPBK
廠商： Advanced Micro Devices, Inc.
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動(dòng)，同步讀/寫閃存
文件頁數(shù)： 4/79頁
文件大?。?/td> 1368K
代理商： AM29BDD160GB17DPBK
2
Am29BDD160G
June 7, 2006
GENERAL DE
S
CRIPTION
The Am2
9
BDD160
is
a
16 Meg
abi
t, 2
.
5 Volt-only
si
n-
gle power
su
pply
bu
r
s
t mode fl
as
h memory dev
i
ce
.
The dev
i
ce c
a
n
b
e conf
i
g
u
red for e
i
ther 1,04
8
,576
word
s
i
n 16-
bi
t mode or 524,2
88
do
ub
le word
s
i
n
3
2-
bi
t mode
.
The dev
i
ce c
a
n
a
l
s
o
b
e progr
a
mmed
i
n
s
t
a
nd
a
rd EPROM progr
a
mmer
s.
The dev
i
ce offer
s
a
conf
i
g
u
r
ab
le
bu
r
s
t
i
nterf
a
ce to 16/
3
2-
bi
t m
i
croproce
s
-
s
or
s
a
nd m
i
crocontroller
s.
To el
i
m
i
n
a
te
bus
content
i
on, e
a
ch dev
i
ce h
as
s
ep
a
r
a
te
ch
i
p en
ab
le (CE#), wr
i
te en
ab
le (WE#)
a
nd o
u
tp
u
t en-
ab
le (OE#) control
s.
Add
i
t
i
on
a
l control
i
np
u
t
s
a
re re-
qui
red for
s
ynchrono
us
bu
r
s
t oper
a
t
i
on
s:
Lo
a
d B
u
r
s
t
Addre
ss
V
a
l
i
d (ADV#),
a
nd Clock (CLK)
.
E
a
ch dev
i
ce re
qui
re
s
only
a
si
n
g
le 2
.
5 or 2
.
6 Volt
power
s
upply
(2
.
5 V to 2
.
75 V) for
b
oth re
a
d
a
nd wr
i
te
f
u
nct
i
on
s.
A 12
.
0-volt V
PP
is
not re
qui
red for progr
a
m
or er
as
e oper
a
t
i
on
s
,
a
ltho
u
gh
a
n
a
cceler
a
t
i
on p
i
n
is
a
v
ai
l
ab
le
i
f f
as
ter progr
a
mm
i
ng perform
a
nce
is
re-
qui
red
.
The dev
i
ce
is
ent
i
rely comm
a
nd
s
et comp
a
t
ib
le w
i
th
the
JEDEC
si
n
g
le-power-
s
upply Fla
s
h
s
tandard
.
The
s
oftw
a
re comm
a
nd
s
et
is
comp
a
t
ib
le w
i
th the
comm
a
nd
s
et
s
of the 5 V Am2
9
F
a
nd
3
V Am2
9
LV
Fl
as
h f
a
m
i
l
i
e
s.
Comm
a
nd
s
a
re wr
i
tten to the comm
a
nd
reg
is
ter
usi
ng
s
t
a
nd
a
rd m
i
croproce
ss
or wr
i
te t
i
m
i
ng
.
Reg
is
ter content
s
s
erve
as
i
np
u
t
s
to
a
n
i
ntern
a
l
s
t
a
te-m
a
ch
i
ne th
a
t control
s
the er
as
e
a
nd progr
a
m-
m
i
ng c
i
rc
ui
try
.
Wr
i
te cycle
s
a
l
s
o
i
ntern
a
lly l
a
tch
a
d-
dre
ss
e
s
a
nd d
a
t
a
needed for the progr
a
mm
i
ng
a
nd
er
as
e oper
a
t
i
on
s.
Re
a
d
i
ng d
a
t
a
o
u
t of the dev
i
ce
is
si
m
i
l
a
r to re
a
d
i
ng from other Fl
as
h or EPROM de-
v
i
ce
s.
The
Unlock Bypa
ss
mode f
a
c
i
l
i
t
a
te
s
f
as
ter progr
a
m-
m
i
ng t
i
me
s
b
y re
qui
r
i
ng only two wr
i
te cycle
s
to pro-
gr
a
m d
a
t
a
i
n
s
te
a
d of fo
u
r
.
The
Si
multaneou
s
Read/Wr
i
te arch
i
tecture
prov
i
de
s
si
m
u
lt
a
neo
us
oper
a
t
i
on
b
y d
i
v
i
d
i
ng the memory
s
p
a
ce
i
nto two
ba
nk
s.
The dev
i
ce c
a
n
b
eg
i
n progr
a
mm
i
ng or
er
asi
ng
i
n one
ba
nk,
a
nd then
si
m
u
lt
a
neo
us
ly re
a
d
from the other
ba
nk, w
i
th zero l
a
tency
.
Th
is
rele
as
e
s
the
s
y
s
tem from w
ai
t
i
ng for the complet
i
on of progr
a
m
or er
as
e oper
a
t
i
on
s.
S
ee
Si
m
u
lt
a
neo
us
Re
a
d/Wr
i
te
Oper
a
t
i
on
s
Overv
i
ew
a
nd Re
s
tr
i
ct
i
on
s
on p
a
ge 1
3.
The dev
i
ce prov
i
de
s
a
256-
b
yte
S
ec
Si
(
S
ecured
Si
l
i
con)
S
ector
w
i
th
a
n one-t
i
me-progr
a
mm
ab
le
(OTP) mech
a
n
is
m
.
In
a
dd
i
t
i
on, the dev
i
ce fe
a
t
u
re
s
s
ever
a
l level
s
of
s
ector
protect
i
on, wh
i
ch c
a
n d
isab
le
b
oth the progr
a
m
a
nd
er
as
e oper
a
t
i
on
s
i
n cert
ai
n
s
ector
s
or
s
ector gro
u
p
s:
Per
sis
tent
S
ector Protect
i
on
is
a
comm
a
nd
s
ector
protect
i
on method th
a
t repl
a
ce
s
the old 12 V con-
trolled protect
i
on method
;
Pa
ss
word
S
ector Protec-
t
i
on
is
a
h
i
ghly
s
oph
is
t
i
c
a
ted protect
i
on method th
a
t
re
qui
re
s
a
p
ass
word
b
efore ch
a
nge
s
to cert
ai
n
s
ector
s
or
s
ector gro
u
p
s
a
re perm
i
tted
;
WP# Hardware Pro-
tect
i
on
prevent
s
progr
a
m or er
as
e
i
n the two o
u
ter-
mo
s
t
8
K
b
yte
s
s
ector
s
of the l
a
rger
ba
nk
.
The dev
i
ce def
au
lt
s
to the Per
sis
tent
S
ector Protect
i
on
mode
.
The c
us
tomer m
us
t then choo
s
e
i
f the
S
t
a
nd
a
rd
or P
ass
word Protect
i
on method
is
mo
s
t de
si
r
ab
le
.
The
WP# H
a
rdw
a
re Protect
i
on fe
a
t
u
re
is
a
lw
a
y
s
a
v
ai
l
ab
le,
i
ndependent of the other protect
i
on method cho
s
en
.
The
Ver
s
at
i
leI/O (V
CCQ
)
fe
a
t
u
re
a
llow
s
the o
u
tp
u
t
volt
a
ge gener
a
ted on the dev
i
ce to
b
e determ
i
ned
bas
ed on the V
IO
level
.
Th
is
fe
a
t
u
re
a
llow
s
th
is
dev
i
ce
to oper
a
te
i
n the 1
.8
V I/O env
i
ronment, dr
i
v
i
ng
a
nd re-
ce
i
v
i
ng
si
gn
a
l
s
to
a
nd from other 1
.8
V dev
i
ce
s
on the
sa
me
bus.
In
a
dd
i
t
i
on,
i
np
u
t
s
a
nd I/O
s
th
a
t
a
re dr
i
ven
extern
a
lly
a
re c
a
p
ab
le of h
a
ndl
i
ng
3.
6 V
.
The ho
s
t
s
y
s
tem c
a
n detect whether
a
progr
a
m or
er
as
e oper
a
t
i
on
is
complete
b
y o
bs
erv
i
ng the RY/BY#
p
i
n,
b
y re
a
d
i
ng the DQ7 (D
a
t
a
# Poll
i
ng), or DQ6 (tog-
gle)
s
tatu
s
b
i
t
s
.
After
a
progr
a
m or er
as
e cycle h
as
b
een completed, the dev
i
ce
is
re
a
dy to re
a
d
a
rr
a
y d
a
t
a
or
a
ccept
a
nother comm
a
nd
.
The
s
ector era
s
e arch
i
tecture
a
llow
s
memory
s
ec-
tor
s
to
b
e er
as
ed
a
nd reprogr
a
mmed w
i
tho
u
t
a
ffect
i
ng
the d
a
t
a
content
s
of other
s
ector
s.
The dev
i
ce
is
f
u
lly
er
as
ed when
s
h
i
pped from the f
a
ctory
.
Hardware data protect
i
on
me
asu
re
s
i
ncl
u
de
a
low
V
CC
detector th
a
t
au
tom
a
t
i
c
a
lly
i
nh
ibi
t
s
wr
i
te oper
a
-
t
i
on
s
d
u
r
i
ng power tr
a
n
si
t
i
on
s.
The
pa
ss
word and
s
oftware
s
ector protect
i
on
fe
a
t
u
re d
isab
le
s
b
oth
progr
a
m
a
nd er
as
e oper
a
t
i
on
s
i
n
a
ny com
bi
n
a
t
i
on of
s
ector
s
of memory
.
Th
is
c
a
n
b
e
a
ch
i
eved
i
n-
s
y
s
tem
a
t
V
CC
level
.
The
Pro
g
ram/Era
s
e
S
u
s
pend/Era
s
e Re
s
ume
fe
a
-
t
u
re en
ab
le
s
the
us
er to p
u
t er
as
e on hold for
a
ny pe-
r
i
od of t
i
me to re
a
d d
a
t
a
from, or progr
a
m d
a
t
a
to,
a
ny
s
ector th
a
t
is
not
s
elected for er
asu
re
.
Tr
u
e
ba
ck-
gro
u
nd er
as
e c
a
n th
us
b
e
a
ch
i
eved
.
The
hardware RE
S
ET# p
i
n
term
i
n
a
te
s
a
ny oper
a
t
i
on
i
n progre
ss
a
nd re
s
et
s
the
i
ntern
a
l
s
t
a
te m
a
ch
i
ne to
re
a
d
i
ng
a
rr
a
y d
a
t
a.
The dev
i
ce offer
s
two power-
sa
v
i
ng fe
a
t
u
re
s.
When
a
ddre
ss
e
s
h
a
ve
b
een
s
t
ab
le for
a
s
pec
i
f
i
ed
a
mo
u
nt of
t
i
me, the dev
i
ce enter
s
the
automat
i
c
s
leep mode
.
The
s
y
s
tem c
a
n
a
l
s
o pl
a
ce the dev
i
ce
i
nto the
s
tandby mode
.
Power con
su
mpt
i
on
is
gre
a
tly re-
d
u
ced
i
n
b
oth the
s
e mode
s.
AMD’
s
Fl
as
h technology com
bi
ne
s
ye
a
r
s
of Fl
as
h
memory m
a
n
u
f
a
ct
u
r
i
ng exper
i
ence to prod
u
ce the
h
i
ghe
s
t level
s
of
qua
l
i
ty, rel
iabi
l
i
ty
a
nd co
s
t effect
i
ve-
ne
ss.
The dev
i
ce electr
i
c
a
lly er
as
e
s
a
ll
bi
t
s
w
i
th
i
n
a
s
ector
si
m
u
lt
a
neo
us
ly v
ia
Fowler-Nordhe
i
m t
u
nnell
i
ng
.
The d
a
t
a
is
progr
a
mmed
usi
ng hot electron
i
n
j
ect
i
on
.
相關(guān)PDF資料
PDF描述
AM29BDD160GB20AKE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20AKF 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20AKI 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20AKK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB20APBE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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