參數(shù)資料
型號: AM29BDD160GB17DPBI
廠商: Advanced Micro Devices, Inc.
英文描述: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述: 16兆位(1 M中的x 16-bit/512畝× 32位),2.5伏的CMOS只突發(fā)模式,雙啟動,同步讀/寫閃存
文件頁數(shù): 24/79頁
文件大?。?/td> 1368K
代理商: AM29BDD160GB17DPBI
22
Am29BDD160G
June 7, 2006
Burst CLK Edge Data Delivery
The Am2
9
BDD160
is
c
a
p
ab
le of del
i
ver
i
ng d
a
t
a
on e
i
-
ther the r
isi
ng or f
a
ll
i
ng edge of CLK
.
To del
i
ver d
a
t
a
on the r
isi
ng edge of CLK,
bi
t 6
i
n the Control Reg
is
ter
(CR6)
is
s
et to 1
.
To del
i
ver d
a
t
a
on the f
a
ll
i
ng edge of
CLK,
bi
t 6
i
n the Control Reg
is
ter
is
cle
a
red to 0
.
The
def
au
lt conf
i
g
u
r
a
t
i
on
is
s
et to the r
isi
ng edge
.
Burst Data Hold Control
The dev
i
ce
is
c
a
p
ab
le of hold
i
ng d
a
t
a
for one CLK
s.
The def
au
lt conf
i
g
u
r
a
t
i
on
is
to hold d
a
t
a
for one CLK
a
nd
is
the only v
a
l
i
d
s
t
a
te
.
Asserting RESET# During A Burst Access
If RE
S
ET#
is
ass
erted low d
u
r
i
ng
a
bu
r
s
t
a
cce
ss
, the
bu
r
s
t
a
cce
ss
is
i
mmed
ia
tely term
i
n
a
ted
a
nd the dev
i
ce
def
au
lt
s
ba
ck to
as
ynchrono
us
re
a
d mode
.
Refer to
RE
S
ET#
:
H
a
rdw
a
re Re
s
et P
i
n
for more
i
nform
a
t
i
on on
the RE
S
ET# f
u
nct
i
on
.
Conf
ig
urat
i
on Re
gis
ter
The Am2
9
BDD160 cont
ai
n
s
a
Conf
i
g
u
r
a
t
i
on Reg
is
ter
for conf
i
g
u
r
i
ng re
a
d
a
cce
ss
e
s.
The Conf
i
g
u
r
a
t
i
on Reg-
is
ter
is
a
cce
ss
ed
b
y the Conf
i
g
u
r
a
t
i
on Reg
is
ter Re
a
d
a
nd the Conf
i
g
u
r
a
t
i
on Reg
is
ter Wr
i
te comm
a
nd
s.
The
Conf
i
g
u
r
a
t
i
on Reg
is
ter doe
s
not occ
u
py
a
ny
a
ddre
ss
-
ab
le memory loc
a
t
i
on,
bu
t r
a
ther,
is
a
cce
ss
ed
b
y the
Conf
i
g
u
r
a
t
i
on Reg
is
ter comm
a
nd
s.
The Conf
i
g
u
r
a
t
i
on
Reg
is
ter
is
re
a
d
ab
le
a
ny t
i
me, however, wr
i
t
i
ng the
Conf
i
g
u
r
a
t
i
on Reg
is
ter
is
re
s
tr
i
cted to t
i
me
s
when the
Em
b
edded Algor
i
thm
is
not
a
ct
i
ve
.
If the
us
er
a
t-
tempt
s
to wr
i
te the Conf
i
g
u
r
a
t
i
on Reg
is
ter wh
i
le the
Em
b
edded Algor
i
thm
is
a
ct
i
ve, the wr
i
te oper
a
t
i
on
is
i
gnored
a
nd the content
s
of the Conf
i
g
u
r
a
t
i
on Reg
is
ter
rem
ai
n
u
nch
a
nged
.
The Conf
i
g
u
r
a
t
i
on Reg
is
ter
is
a
16
bi
t d
a
t
a
f
i
eld wh
i
ch
is
a
cce
ss
ed
b
y DQ15–DQ0
.
D
a
t
a
on DQ
3
1–DQ16
is
i
gnored d
u
r
i
ng
a
wr
i
te oper
a
t
i
on when WORD# = V
IL
.
D
u
r
i
ng
a
re
a
d oper
a
t
i
on, DQ
3
1–DQ16 ret
u
rn
s
a
ll ze-
roe
s.
T
ab
le
9
s
how
s
the Conf
i
g
u
r
a
t
i
on Reg
is
ter
.
Al
s
o,
Conf
i
g
u
r
a
t
i
on Reg
is
ter re
a
d
s
oper
a
te the
sa
me
as
A
u
-
to
s
elect comm
a
nd re
a
d
s.
When the comm
a
nd
is
is
-
su
ed, the
ba
nk
a
ddre
ss
is
l
a
tched
a
long w
i
th the
comm
a
nd
.
Re
a
d
s
oper
a
t
i
on
s
to the
ba
nk th
a
t w
as
s
pec
i
f
i
ed d
u
r
i
ng the Conf
i
g
u
r
a
t
i
on Reg
is
ter re
a
d com-
m
a
nd ret
u
rn Conf
i
g
u
r
a
t
i
on Reg
is
ter content
s.
Re
a
d
oper
a
t
i
on
s
to the other
ba
nk ret
u
rn fl
as
h memory d
a
t
a.
E
i
ther
ba
nk
a
ddre
ss
is
perm
i
tted when wr
i
t
i
ng the
Conf
i
g
u
r
a
t
i
on Reg
is
ter re
a
d comm
a
nd
.
Table 9
.
Conf
ig
urat
i
on Re
gis
ter Def
i
n
i
t
i
on
s
CR15
CR14
CR1
3
CR12
CR11
CR10
CR
9
CR
8
RM
Re
s
erved
IAD
3
IAD2
IAD1
IAD0
DOC
WC
CR7
CR6
CR5
CR4
CR
3
CR2
CR1
CR0
B
S
CC
Re
s
erved
Re
s
erved
Re
s
erved
BL2
BL1
BL0
Conf
ig
urat
i
on Re
gis
ter
CR15 = Read Mode (RM)
0 =
S
ynchrono
us
B
u
r
s
t Re
a
d
s
En
ab
led
1 = A
s
ynchrono
us
Re
a
d
s
En
ab
led (Def
au
lt)
CR14 = Re
s
erved for Future Enhancement
s
The
s
e
bi
t
s
a
re re
s
erved for f
u
t
u
re
us
e
.
S
et the
s
e
bi
t
s
to “0”
.
相關(guān)PDF資料
PDF描述
AM29BDD160GB17DPBK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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