參數(shù)資料
型號(hào): AM29BDD160GB17DKI
廠商: Advanced Micro Devices, Inc.
英文描述: 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述: 16兆位(1 M中的x 16-bit/512畝× 32位),2.5伏的CMOS只突發(fā)模式,雙啟動(dòng),同步讀/寫閃存
文件頁(yè)數(shù): 16/79頁(yè)
文件大?。?/td> 1368K
代理商: AM29BDD160GB17DKI
14
Am29BDD160G
June 7, 2006
re
a
d-wh
i
le-progr
a
m
a
nd re
a
d-wh
i
le-er
as
e c
u
rrent
s
pec
i
f
i
c
a
t
i
on
s.
Si
m
u
lt
a
neo
us
re
a
d/wr
i
te oper
a
t
i
on
s
a
re v
a
l
i
d for
b
oth
the m
ai
n Fl
as
h memory
a
rr
a
y
a
nd the
S
ec
Si
OTP
s
ec-
tor
.
Si
m
u
lt
a
neo
us
oper
a
t
i
on
is
d
isab
led d
u
r
i
ng the CFI
a
nd P
ass
word Progr
a
m/Ver
i
fy oper
a
t
i
on
s.
PPB Pro-
gr
a
m/Er
as
e oper
a
t
i
on
s
a
nd the P
ass
word Unlock op-
er
a
t
i
on perm
i
t re
a
d
i
ng d
a
t
a
from the l
a
rge (75
%
)
ba
nk
wh
i
le re
a
d
i
ng the oper
a
t
i
on
s
t
a
t
us
of the
s
e comm
a
nd
s
from the
s
m
a
ll (25
%
)
ba
nk
.
Table
3.
Top Boot Bank
S
elect
Table 4
.
Bottom Boot Bank
S
elect
Wr
i
t
i
n
g
Command
s
/Command
S
equence
s
To wr
i
te
a
comm
a
nd or comm
a
nd
s
e
qu
ence (wh
i
ch
i
n-
cl
u
de
s
progr
a
mm
i
ng d
a
t
a
to the dev
i
ce
a
nd er
asi
ng
s
ector
s
of memory), the
s
y
s
tem m
us
t dr
i
ve WE#
a
nd
CE# to V
IL
,
a
nd OE# to V
IH
.
For progr
a
m oper
a
t
i
on
s
,
i
n the x
3
2-mode the dev
i
ce
a
ccept
s
progr
a
m d
a
t
a
i
n
3
2-
bi
t word
s
a
nd
i
n the x16
mode the dev
i
ce
a
ccept
s
progr
a
m d
a
t
a
i
n 16-
bi
t
word
s.
The dev
i
ce fe
a
t
u
re
s
a
n
Unlock Bypa
ss
mode to f
a
c
i
l
i
-
t
a
te f
as
ter progr
a
mm
i
ng
.
Once the dev
i
ce enter
s
the
Unlock Byp
ass
mode, only two wr
i
te cycle
s
a
re re-
qui
red to progr
a
m
a
word or
b
yte,
i
n
s
te
a
d of fo
u
r
.
The
S
ector Er
as
e
a
nd Progr
a
m
Sus
pend Comm
a
nd
s
ec-
t
i
on h
as
det
ai
l
s
on progr
a
mm
i
ng d
a
t
a
to the dev
i
ce
usi
ng
b
oth
s
t
a
nd
a
rd
a
nd Unlock Byp
ass
comm
a
nd
s
e-
qu
ence
s.
An er
as
e oper
a
t
i
on c
a
n er
as
e one
s
ector, m
u
lt
i
ple
s
ec-
tor
s
, or the ent
i
re dev
i
ce
.
T
ab
le
s
12
a
nd 1
3
i
nd
i
c
a
te
the
a
ddre
ss
s
p
a
ce th
a
t e
a
ch
s
ector occ
u
p
i
e
s.
A “
s
ec-
tor
a
ddre
ss
” con
sis
t
s
of the
a
ddre
ss
bi
t
s
re
qui
red to
u
n
iqu
ely
s
elect
a
s
ector
.
The “Comm
a
nd Def
i
n
i
t
i
on
s
s
ect
i
on h
as
det
ai
l
s
on er
asi
ng
a
s
ector or the ent
i
re
ch
i
p, or
sus
pend
i
ng/re
su
m
i
ng the er
as
e oper
a
t
i
on
.
After the
s
y
s
tem wr
i
te
s
the
au
to
s
elect comm
a
nd
s
e-
qu
ence, the dev
i
ce enter
s
the
au
to
s
elect mode
.
The
s
y
s
tem c
a
n then re
a
d
au
to
s
elect code
s
from the
i
nter-
n
a
l reg
is
ter (wh
i
ch
is
s
ep
a
r
a
te from the memory
a
rr
a
y)
on DQ7–DQ0
.
S
t
a
nd
a
rd re
a
d cycle t
i
m
i
ng
a
ppl
i
e
s
i
n
th
is
mode
.
Refer to the “A
u
to
s
elect Mode”
s
ect
i
on for
more
i
nform
a
t
i
on
.
I
CC2
i
n the DC Ch
a
r
a
cter
is
t
i
c
s
t
ab
le repre
s
ent
s
the
a
c-
t
i
ve c
u
rrent
s
pec
i
f
i
c
a
t
i
on for er
as
e or progr
a
m mode
s.
The
AC Ch
a
r
a
cter
is
t
i
c
s
s
ect
i
on cont
ai
n
s
t
i
m
i
ng
s
pec
i
f
i
-
c
a
t
i
on t
ab
le
s
a
nd t
i
m
i
ng d
ia
gr
a
m
s
for er
as
e or pro-
gr
a
m oper
a
t
i
on
s.
Accelerated Pro
g
ram and Era
s
e Operat
i
on
s
The dev
i
ce offer
s
a
cceler
a
ted progr
a
m/er
as
e oper
a
-
t
i
on
s
thro
u
gh the ACC p
i
n
.
When the
s
y
s
tem
ass
ert
s
V
HH
(12V) on the ACC p
i
n, the dev
i
ce
au
tom
a
t
i
c
a
lly
enter
s
the Unlock Byp
ass
mode
.
The
s
y
s
tem m
a
y
then wr
i
te the two-cycle Unlock Byp
ass
progr
a
m com-
m
a
nd
s
e
qu
ence to do
a
cceler
a
ted progr
a
mm
i
ng
.
The
dev
i
ce
us
e
s
the h
i
gher volt
a
ge on the ACC p
i
n to
a
c-
celer
a
te the oper
a
t
i
on
.
A
s
ector th
a
t
is
b
e
i
ng protected
w
i
th the WP# p
i
n w
i
ll
s
t
i
ll
b
e protect d
u
r
i
ng
a
cceler
a
ted
progr
a
m or Er
as
e
.
Note th
a
t the ACC p
i
n m
us
t not
b
e
a
t V
HH
d
u
r
i
ng
a
ny oper
a
t
i
on other th
a
n
a
cceler
a
ted
progr
a
mm
i
ng, or dev
i
ce d
a
m
a
ge m
a
y re
su
lt
.
Auto
s
elect Funct
i
on
s
If the
s
y
s
tem wr
i
te
s
the
au
to
s
elect comm
a
nd
s
e-
qu
ence, the dev
i
ce enter
s
the
au
to
s
elect mode
.
The
s
y
s
tem c
a
n then re
a
d
au
to
s
elect code
s
from the
i
nter-
n
a
l reg
is
ter (wh
i
ch
is
s
ep
a
r
a
te from the memory
a
rr
a
y)
on DQ7–DQ0
.
S
t
a
nd
a
rd re
a
d cycle t
i
m
i
ng
s
a
pply
i
n
th
is
mode
.
Refer to the A
u
to
s
elect Mode
a
nd A
u
to
s
e-
lect Comm
a
nd
S
e
qu
ence
s
ect
i
on
s
for more
i
nform
a
-
t
i
on
.
Automat
i
c
S
leep Mode (A
S
M)
The
au
tom
a
t
i
c
s
leep mode m
i
n
i
m
i
ze
s
Fl
as
h dev
i
ce en-
ergy con
su
mpt
i
on
.
Wh
i
le
i
n
as
ynchrono
us
mode, the
dev
i
ce
au
tom
a
t
i
c
a
lly en
ab
le
s
th
is
mode when
a
d-
dre
ss
e
s
rem
ai
n
s
t
ab
le for t
ACC
+ 60 n
s.
The
au
tom
a
t
i
c
s
leep mode
is
i
ndependent of the CE#, WE#
a
nd OE#
control
si
gn
a
l
s.
S
t
a
nd
a
rd
a
ddre
ss
a
cce
ss
t
i
m
i
ng
s
pro-
v
i
de new d
a
t
a
when
a
ddre
ss
e
s
a
re ch
a
nged
.
Wh
i
le
i
n
s
leep mode, o
u
tp
u
t d
a
t
a
is
l
a
tched
a
nd
a
lw
a
y
s
a
v
ai
l-
ab
le to the
s
y
s
tem
.
Wh
i
le
i
n
s
ynchrono
us
mode, the
dev
i
ce
au
tom
a
t
i
c
a
lly en
ab
le
s
th
is
mode when e
i
ther
the f
i
r
s
t
a
ct
i
ve CLK level
is
gre
a
ter th
a
n t
ACC
or the
CLK r
u
n
s
s
lower th
a
n 5 MHz
.
Note th
a
t
a
new
bu
r
s
t
oper
a
t
i
on
is
re
qui
red to prov
i
de new d
a
t
a.
I
CC
8
i
n the “DC Ch
a
r
a
cter
is
t
i
c
s
s
ect
i
on of p
a
ge 5
3
rep-
re
s
ent
s
the
au
tom
a
t
i
c
s
leep mode c
u
rrent
s
pec
i
f
i
c
a
-
t
i
on
.
S
tandby Mode
When the
s
y
s
tem
is
not re
s
pond
i
ng or wr
i
t
i
ng to the
dev
i
ce,
i
t c
a
n pl
a
ce the dev
i
ce
i
n the
s
t
a
nd
b
y mode
.
In
th
is
mode, c
u
rrent con
su
mpt
i
on
is
gre
a
tly red
u
ced,
a
nd the o
u
tp
u
t
s
a
re pl
a
ced
i
n the h
i
gh
i
mped
a
nce
s
t
a
te,
i
ndependent of the OE#
i
np
u
t
.
The dev
i
ce enter
s
the CMO
S
s
t
a
nd
b
y mode when the
CE#
a
nd RE
S
ET#
i
np
u
t
s
a
re
b
oth held
a
t Vcc
±
0
.
2 V
.
The dev
i
ce re
qui
re
s
s
t
a
nd
a
rd
a
cce
ss
t
i
me (t
CE
) for
re
a
d
a
cce
ss
,
b
efore
i
t
is
re
a
dy to re
a
d d
a
t
a.
Bank
B
a
nk 1
B
a
nk 2
A1
8
:A17
00
01, 1X
Bank
B
a
nk 1
B
a
nk 2
A1
8
0X, 10
11
相關(guān)PDF資料
PDF描述
AM29BDD160GB17DKK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB17DPBE 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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AM29BDD160GB17DPBI 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
AM29BDD160GB17DPBK 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
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