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參數(shù)資料
| 型號： | AM29BDD160GB17CPBF |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 16兆位（1 M中的x 16-bit/512畝× 32位），2.5伏的CMOS只突發(fā)模式，雙啟動，同步讀/寫閃存 |
| 文件頁數(shù)： | 52/79頁 |
| 文件大?。?/td> | 1368K |
| 代理商： | AM29BDD160GB17CPBF |
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50
Am29BDD160G
June 7, 2006
DQ6: To
gg
le B
i
t I
Toggle B
i
t I on DQ6
i
nd
i
c
a
te
s
whether
a
n Em
b
edded
Progr
a
m or Er
as
e
a
lgor
i
thm
is
i
n progre
ss
or complete,
or whether the dev
i
ce h
as
entered the Er
as
e
Sus
pend
mode
.
Toggle B
i
t I m
a
y
b
e re
a
d
a
t
a
ny
a
ddre
ss
,
a
nd
is
v
a
l
i
d
a
fter the r
isi
ng edge of the f
i
n
a
l WE# p
u
l
s
e
i
n the
comm
a
nd
s
e
qu
ence (pr
i
or to the progr
a
m or er
as
e op-
er
a
t
i
on),
a
nd d
u
r
i
ng the
s
ector er
as
e t
i
me-o
u
t
.
D
u
r
i
ng
a
n Em
b
edded Progr
a
m or Er
as
e
a
lgor
i
thm op-
er
a
t
i
on, two
i
mmed
ia
tely con
s
ec
u
t
i
ve re
a
d cycle
s
to
a
ny
a
ddre
ss
c
aus
e DQ6 to toggle
.
When the oper
a
t
i
on
is
complete, DQ6
s
top
s
toggl
i
ng
.
For
as
ynchrono
us
mode, e
i
ther OE# or CE# c
a
n
b
e
us
ed to control the
re
a
d cycle
s.
For
s
ynchrono
us
mode, the r
isi
ng edge of
ADV#
is
us
ed or the r
isi
ng edge of clock wh
i
le ADV#
is
Low
.
After
a
n er
as
e comm
a
nd
s
e
qu
ence
is
wr
i
tten,
i
f
a
ll
s
ec-
tor
s
s
elected for er
asi
ng
a
re protected, DQ6 toggle
s
for
a
pprox
i
m
a
tely 100
μs
, then ret
u
rn
s
to re
a
d
i
ng
a
rr
a
y
d
a
t
a.
If not
a
ll
s
elected
s
ector
s
a
re protected, the Em-
b
edded Er
as
e
a
lgor
i
thm er
as
e
s
the
u
nprotected
s
ec-
tor
s
,
a
nd
i
gnore
s
the
s
elected
s
ector
s
th
a
t
a
re protected
.
The
s
y
s
tem c
a
n
us
e DQ6
a
nd DQ2 together to deter-
m
i
ne whether
a
s
ector
is
a
ct
i
vely er
asi
ng or
is
er
as
e-
sus
pended
.
When the dev
i
ce
is
a
ct
i
vely er
asi
ng
(th
a
t
is
, the Em
b
edded Er
as
e
a
lgor
i
thm
is
i
n progre
ss
),
DQ6 toggle
s.
When the dev
i
ce enter
s
the Er
as
e
Sus
-
pend mode, DQ6
s
top
s
toggl
i
ng
.
However, the
s
y
s
tem
m
us
t
a
l
s
o
us
e DQ2 to determ
i
ne wh
i
ch
s
ector
s
a
re
er
asi
ng or er
as
e-
sus
pended
.
Altern
a
t
i
vely, the
s
y
s
tem
c
a
n
us
e DQ7 (
s
ee the
subs
ect
i
on on
DQ7
:
D
a
t
a
# Poll-
i
ng
)
.
If
a
progr
a
m
a
ddre
ss
f
a
ll
s
w
i
th
i
n
a
protected
s
ector,
DQ6 toggle
s
for
a
pprox
i
m
a
tely 1
μs
a
fter the progr
a
m
comm
a
nd
s
e
qu
ence
is
wr
i
tten, then ret
u
rn
s
to re
a
d
i
ng
a
rr
a
y d
a
t
a.
DQ6
a
l
s
o toggle
s
d
u
r
i
ng the er
as
e-
sus
pend-progr
a
m
mode,
a
nd
s
top
s
toggl
i
ng once the Em
b
edded Pro-
gr
a
m
a
lgor
i
thm
is
complete
.
T
ab
le 2
3
s
how
s
the o
u
tp
u
t
s
for Toggle B
i
t I on DQ6
.
F
i
g
u
re 7
s
how
s
the toggle
bi
t
a
lgor
i
thm
i
n flowch
a
rt
form,
a
nd the
s
ect
i
on
Re
a
d
i
ng Toggle B
i
t
s
DQ6/DQ2
expl
ai
n
s
the
a
lgor
i
thm
.
F
i
g
u
re 25
i
n the
AC Ch
a
r
a
cter-
is
t
i
c
s
s
ect
i
on
s
how
s
the toggle
bi
t t
i
m
i
ng d
ia
gr
a
m
s.
F
i
g-
u
re 25
s
how
s
the d
i
fference
s
b
etween DQ2
a
nd DQ6
i
n
gr
a
ph
i
c
a
l form
.
S
ee
a
l
s
o the
subs
ect
i
on on
DQ2
:
Tog-
gle B
i
t II
.
F
i
g
u
re 27
s
how
s
the t
i
m
i
ng d
ia
gr
a
m for
s
yn-
chrono
us
toggle
bi
t
s
t
a
t
us.
DQ2: To
gg
le B
i
t II
The “Toggle B
i
t II” on DQ2, when
us
ed w
i
th DQ6,
i
nd
i
-
c
a
te
s
whether
a
p
a
rt
i
c
u
l
a
r
s
ector
is
a
ct
i
vely er
asi
ng
(th
a
t
is
, the Em
b
edded Er
as
e
a
lgor
i
thm
is
i
n progre
ss
),
or whether th
a
t
s
ector
is
er
as
e-
sus
pended
.
Toggle B
i
t
II
is
v
a
l
i
d
a
fter the r
isi
ng edge of the f
i
n
a
l WE# p
u
l
s
e
i
n
the comm
a
nd
s
e
qu
ence
.
DQ2 toggle
s
when the
s
y
s
tem perform
s
two
i
mmed
i
-
a
tely con
s
ec
u
t
i
ve re
a
d
s
a
t
a
ddre
ss
e
s
w
i
th
i
n tho
s
e
s
ec-
tor
s
th
a
t h
a
ve
b
een
s
elected for er
asu
re
.
(For
as
ynchrono
us
mode, e
i
ther OE# or CE# c
a
n
b
e
us
ed
to control the re
a
d cycle
s.
For
s
ynchrono
us
mode,
ADV#
is
us
ed
.
) B
u
t DQ2 c
a
nnot d
is
t
i
ng
uis
h whether
DQ7 = D
a
t
a
Ye
s
No
No
DQ5 = 1
No
Ye
s
Ye
s
FAIL
PA
SS
Re
a
d DQ7–DQ0
Addr = VA
Re
a
d DQ7–DQ0
Addr = VA
DQ7 = D
a
t
a
S
TART
Notes:
1
.
VA = V
a
l
i
d
a
ddre
ss
for progr
a
mm
i
ng
.
D
u
r
i
ng
a
s
ector
er
as
e oper
a
t
i
on,
a
v
a
l
i
d
a
ddre
ss
is
a
n
a
ddre
ss
w
i
th
i
n
a
ny
s
ector
s
elected for er
asu
re
.
D
u
r
i
ng ch
i
p er
as
e,
a
v
a
l
i
d
a
ddre
ss
is
a
ny non-protected
s
ector
a
ddre
ss.
2
.
DQ7
s
ho
u
ld
b
e rechecked even
i
f DQ5 = “1”
b
ec
aus
e
DQ7 m
a
y ch
a
nge
si
m
u
lt
a
neo
us
ly w
i
th DQ5
.
F
ig
ure 6
.
Data# Poll
i
n
g
Al
g
or
i
thm
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB17CPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17CPBK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17DKF | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17DKI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB17DKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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