Table 6-57. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V]<" />
參數(shù)資料
型號(hào)： AM1808BZWT4
廠商： Texas Instruments
文件頁(yè)數(shù)： 54/264頁(yè)
文件大?。?/td> 0K
描述： IC ARM9 MPU 361NFBGA
標(biāo)準(zhǔn)包裝： 90
系列： ARM9
處理器類型： ARM 微處理器
速度： 456MHz
電壓： 1.25 V ~ 1.35 V
安裝類型： 表面貼裝
封裝/外殼： 361-LFBGA
供應(yīng)商設(shè)備封裝： 361-NFBGA（16x16）
包裝： 托盤(pán)
其它名稱： 296-28241
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-57. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V](1) (see Figure 6-32)
1.3V, 1.2V
1.1V
NO.
UNIT
MIN
MAX
MIN
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P or 20(2)(3)
2P or 25(2) (4)
ns
Pulse duration, CLKR/X high or
3
tw(CKRX)
CLKR/X ext
P - 1(5)
P - 1(6)
ns
CLKR/X low
CLKR int
15
18
Setup time, external FSR high before
5
tsu(FRH-CKRL)
ns
CLKR low
CLKR ext
5
CLKR int
6
Hold time, external FSR high after
6
th(CKRL-FRH)
ns
CLKR low
CLKR ext
3
CLKR int
15
18
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
ns
CLKR ext
5
CLKR int
3
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
ns
CLKR ext
3
CLKX int
15
18
Setup time, external FSX high before
10
tsu(FXH-CKXL)
ns
CLKX low
CLKX ext
5
CLKX int
6
Hold time, external FSX high after
11
th(CKXL-FXH)
ns
CLKX low
CLKX ext
3
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2)
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3)
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4)
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(5)
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
(6)
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Table 6-58. Timing Requirements for McBSP1 [1.0V](1) (see Figure 6-32)
1.0V
NO.
UNIT
MIN
MAX
2
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P or 26.6(2)(3)
ns
3
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P - 1(4)
ns
CLKR int
21
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
ns
CLKR ext
10
CLKR int
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
ns
CLKR ext
3
CLKR int
21
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
ns
CLKR ext
10
CLKR int
3
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
ns
CLKR ext
3
CLKX int
21
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
ns
CLKX ext
10
CLKX int
6
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
ns
CLKX ext
3
(1)
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2)
P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.
(3)
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4)
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
Copyright 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
147
Product Folder Links: AM1808
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