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參數(shù)資料
| 型號： | ALD500SWCL |
| 廠商： | Advanced Linear Devices Inc |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DUAL 16WSOIC |
| 標(biāo)準(zhǔn)包裝： | 46 |
| 位數(shù)： | 16 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 10mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | * |
| 其它名稱： | 1014-1186 |
10
Advanced Linear Devices
ALD500AU/ALD500A/ALD500
EQUATIONS AND DERIVATIONS
Dual Slope Analog Processor equations and derivations
are as follows:
1
60Hz
2.0
20x10-6
=
~
=
~
=
~
DESIGN EXAMPLES
We now apply these equations in the following
design examples.
Design Example 1:
1. Pick resolution = 16 bit.
2. Pick tINT = 4x
= 4 x 16.6667 msec.
3. Pick clock period = 1.08507
s and number of counts
4. Pick VINMAX value, e.g., VINMAX = 2.0 V
I BMAX = 20A
RINT =
= 100 k
5. Applying equation (3) to calculate CINT:
6. Pick CREF and CAZ ≥ CINT: CREF
CAZ
0.33
F
7. Pick tDINT = 2 x tINT = 133.3334 msec
8. Calculate VREF
VINTMAX . CINT . RINT
tDINT MAX
=
4 x 0.33 x 10-6 x 100 x 103
133.3334 x 10-3
0.99V
1.00V
= 0.0666667 sec.
V
1
RINT . CINT
VIN(t)dt =
∫
0
tINT
tDINT
VIN = VREF .
tINT
1
tINT . VIN =
VREF . tDINT
(2a)
(2)
(1)
CINT =
VINT
tINT . IB
(3)
RINT =
VINMAX
IBMAX
(4)
For VIN(t) = VIN (constant):
From equation (2a),
OR
Rearranging equations (3) and (4):
At VINT = VINT MAX, equation (6) becomes:
Combining (6a) and (7):
In equation (5b), substituting equation (8) for tINT:
For tDINT MAX = 2 x tINT,
equation (9) becomes:
VIN MAX . tINT
tDINT MAX
VIN . tINT
tDINT
(5a)
(5b)
tINT =
CINT . VINT
IB
(6)
IBMAX =
VINMAX
RINT
(7)
VREF =
... tINT =
CINT . VINTMAX . RINT
VINMAX
(8)
VIN MAX .
tDINT MAX
VREF =
CINT . VINTMAX . RINT
VIN MAX
=
CINT . VINTMAX . RINT
tDINT MAX
(9)
VREF =
CINT . VINTMAX . RINT
2tINT
(10)
RINT . CINT
VREF . tDINT
RINT . CINT
...
tINT = CINT
. VINTMAX
IBMAX
and
At VINMAX, the current IB is also at a maximum level,
for a given RINT value:
VIN
IB
=
(6a)
CINT = (0.0666667)(20x10-6)/4 where VINT = 4.0V
0.33
F
Design Example 2:
1. Select resolution of 17 bit. Total number of
counts during tINT is131,072.
2. We can pick tINT of 16.6667 msec. x 5 = 83.3333 msec.
or alternately, pick t INT equal
16.6667 msec. x 6 = 100.00 msec.
(for 60 Hz rejection)
which is t INT = 20.00 msec. x 5
Therefore, using t INT = 100 msec. would achieve
both 50 Hz and 60 Hz cycle noise rejection. For this
example, the following calculations would assume
t INT of 100 msec. Now select period equal to
0.5425
sec. (clock frequency of 1.8432 MHz)
= 66.6667ms
=
~
= 100.00 msec. (for 50 Hz rejection)
0.0666667
1.08507x10-6
over tINT =
= 61440
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