參數(shù)資料
型號(hào): AL3201
廠商: Electronic Theatre Controls, Inc.
元件分類(lèi): 圓形連接器
英文描述: Circular Connector; No. of Contacts:19; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-19
中文描述: 可控硅,或單芯片混響
文件頁(yè)數(shù): 6/10頁(yè)
文件大?。?/td> 256K
代理商: AL3201
Alesis Semiconductor
DS3201-0802 12555 J efferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
-
6
-
MAC Instruction Word
Bit #
31
S: Sign bit for multiplier coefficient.
C[7:1]: Multiplier coefficient, 2’s complement.
C[7:0]: Chorus instruction. Only the 7 MSBs
are used as multiplier coefficients. The LSB is
used in chorus mode. If I[5] is set, C[7:0] is:
C
Chorus/ Xfade select:
1: Pass LFO address to address
generator & select chorus coefficient.
0: Mask LFO address to address
generator & select crossfade coefficient.
1’s complement the LFO address sign
bit.
1
5
1’s complement the LFO coefficient.
4
1’s complement the LFO address.
LFO latch. 1: Latch in new LFO data;
0: Hold last LFO data.
2
2:1
LFO select.
0
LFO sine/ cosine select. 1: Cos; 0: Sin.
22
W: Write select.
3, 4
I[5:0]: Instruction field.
I
Chorus select (When set, MAC
coefficient is LFO block output, LFO
address offset added to DRAM
address).
4
Clock register C.
3
3
Clock register B.
4
2
Reserved – set to zero.
Description
Description
7
6
3
30:23
Description
5
I[1:0]
11
10
01
00
Instruction
Acc = Prod + Acc
6
Acc = Prod + C
3
Acc = Prod + B
5
Acc = Prod + 0
21:16
1:0
MAC
product
instruc-
tion.
15:0
A[15:0]: Multiplicand address.
7, 8
(Currently
only lower 15 bits used; reserve MSB for
future expansion.)
Address 0x0000 = LeftIn/ Out;
Address 0x0001 = RightIn/ Out.
Notes:
1.
This complement is only for the MSB, and sign-
extension bits are not affected.
Upon latching new data, the LFO registers will
store
the
lower
or
sinusoid/ triangle waves, and the lower or upper
LFO pairs’ crossfade coefficient. I.e. there are
two pairs of registers; LFO 0/ 1’s sinusoid
/ triangle/ crossfade will be latched together, and
LFO 2/ 3’s sinusoid/ triangle/ crossfade will be
latched together.
The LeftOut, RightOut, and C registers are in
parallel with the accumulator, and will contain
the same value as the accumulator if clocked at
the end of the tick.
A write to DRAM stores the last tick’s results into
address A. Writes to LeftOut or RightOut should
use the Acc = Product + Acc instruction with the
multiplier coefficient set to 0 to pass all bits
unaltered.
2.
upper
LFO
pairs’
3.
4.
5.
Register B, if clocked at the end of the tick, will
store the value of the current tick’s multiplicand.
When a read is executed, B latches LeftIn,
RightIn, or DRAM. When a write is executed, B
latches the accumulator from the last tick.
The accumulator contains the result from the
last instruction tick, and is updated at the end of
the current instruction tick.
The internal DRAM address offset automatically
decrements by 1 every word clock period.
Because addresses 0x0000 and 0x0001 are
being used to access the left and right channels,
those DRAM memory locations may not be
directly written to or read from.
6.
7.
8.
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