參數(shù)資料
型號： AKD4562(AKD4562)
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Evaluation board Rev.A for AK4562
中文描述： 評價(jià)AK4562板版本A
文件頁數(shù)： 6/30頁
文件大?。?/td> 396K
代理商： AKD4562(AKD4562)
ASAHI KASEI
[AKD4562]
<KM061600>
’00/06
- 6 -
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data.
Digital signals generated by AKD43XX are used. PORT3 is used for the interface with AKD43XX. Master
clock is sent from AKD4562 to AKD43XX and BCLK, LRCK, SDTI are sent from AKD43XX to
AKD4562. Nothing should be connected to PORT4. In case of using external clock through a BNC
connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP13
CLK
JP12
DIR
JP6
X_BCLK
64fs
32fs
JP8
BCLK
JP14
XTE
JP7
LRCK
DIR
ADC
D
E
X
GND
VD
JP11
SDTI
DIR
ADC
DIR
ADC
3) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3. Nothing should be connected to PORT4. In case of using
external clock through a BNC connector (J1), select EXT on JP13 (CLK) and short JP14 (XTE).
JP13
CLK
JP12
DIR
JP6
X_BCLK
64fs
32fs
JP8
BCLK
JP14
XTE
JP7
LRCK
DIR
ADC
D
E
X
GND
VD
JP11
SDTI
DIR
ADC
DIR
ADC
4) Evaluation of D/A using DIR. (Optical link)
PORT4 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3. DIR (CS8412) corresponds to only I
2
S compatible mode or 16 bit LSB justified.
JP13
CLK
JP12
DIR
JP6
X_BCLK
64fs
32fs
JP8
BCLK
JP14
XTE
JP7
LRCK
DIR
ADC
D
E
X
GND
VD
JP11
SDTI
DIR
ADC
DIR
ADC
相關(guān)PDF資料
PDF描述
AKD4562.(AKD4562) Evaluation board Rev.A for AK4562
AKD5351 EVALUATION BOARD REV.B FOR AK5351
AKD5352 EVALUATION BOARD REV.B FOR AK5352
AKD5353 EVALUATION BOARD REV.B FOR AK5353
AKD5354 EVALUATION BOARD REV.A FOR AK5354
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AKD4565 制造商:AKM 制造商全稱:AKM 功能描述:Evaluation board Rev.A for AK4565
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