
ASAHI KASEI
[AKD4551]
<KM062000>
’00/3
- 4 -
2) Evaluation of D/A using A/D converted data from ideal sine wave generated by ROM data.
Digital signals generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master
clock is sent from AKD4551 to AKD43XX and SCLK, LRCK, SDTI are sent from AKD43XX to
AKD4551. Nothing should be connected to PORT3. In case of using external clock through a BNC
connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE).
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs
3) Evaluation of D/A using A/D converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT1. Nothing should be connected to PORT3. In case of using
external clock through a BNC connector (J5), select EXT on JP12 (XTI) and short JP10 (XTE).
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs
4) Evaluation of D/A using DIR. (Optical link)
PORT3 (TORX176) is used. DIR generates MCLK, SCLK, LRCK and SDATA from the received data
through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be
connected to PORT1/PORT2.
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs
5) Evaluation of A/D using D/A converted data.
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT1. Nothing should be connected to PORT3.
JP12
XTI
JP14
DIR
JP6
SCLK
DIR
ADC
JP8
LRCK
JP10
XTE
JP13
X_SCLK
DIR
ADC
D
X
E
OFF
ON
JP9
SDTI
DIR
ADC
64fs
32fs